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User's Guide

SLUU323 – JUNE 2008

Using theTPS51200 EVM Sink/Source DDR Termination

Regulator

Contents

1 Introduction ................................................................................................................... 2

2 Description .................................................................................................................... 2

3 Electrical Performance Specifications ..................................................................................... 3

4 Test Setup .................................................................................................................... 6

5 Test Procedure ............................................................................................................... 9

6 Performance Data and Typical Characteristic Curves................................................................. 14

7 EVM Assembly ............................................................................................................. 15

8 List of Materials ............................................................................................................. 18

9 References .................................................................................................................. 18

List of Figures

1 EVM Schematic .............................................................................................................. 4

2 EVM Schematic .............................................................................................................. 5

3 Recommended Test Setup ................................................................................................. 7

4 Control Loop Measurement Setup ....................................................................................... 13

5 DDR3 VTT Sink/Source Load Regulation .............................................................................. 14

6 DDR3 VTTREF Sink/Source Load Regulation ........................................................................ 14

7 VTT Source 1 A, Enable Start Up ........................................................................................ 14

8 VTT Source 1 A, Enable Shutdown ...................................................................................... 14

9 DDR3 VTT Sink/Source Transient ....................................................................................... 15

10 Bode Plot for DDR3 Application .......................................................................................... 15

11 Bottom Side Silkscreen (Top View) ...................................................................................... 15

12 Bottom Side Assembly..................................................................................................... 16

13 Bottom Side Copper ....................................................................................................... 16

14 Top Side Copper ........................................................................................................... 17

List of Tables

1 TPS51120 Performance Specification Summary ........................................................................ 3

2 I/O and Jumper Connections ............................................................................................... 6

3 Test Points .................................................................................................................... 8

4 List of Materials ............................................................................................................. 18

SLUU323 – JUNE 2008 Using theTPS51200 EVM Sink/Source DDR Termination Regulator 1

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Summary of content (20 pages)

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User's Guide SLUU323 – JUNE 2008 Using theTPS51200 EVM Sink/Source DDR Termination Regulator 1 2 3 4 5 6 7 8 9 Contents Introduction ................................................................................................................... 2 Description .................................................................................................................... 2 Electrical Performance Specifications .....................................................................................
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Introduction 1 www.ti.com Introduction The TPS51200EVM evaluation board, HPA322A is designed to evaluate the performance and characteristics of TI's cost optimized DDR/DDR2/DDR3/LP DDR3 VTT termination regulator, the TPS51200. 1.1 Background The TPS51200 is designed to provide proper termination voltage and a 10-mA buffered reference voltage for DDR memory which covered DDR (2.5 V/1.25 V), DDR2 (1.8 V/0.9 V), DDR3 (1.5 V/0.75 V), LP DDR3 (1.2 V/0.
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Electrical Performance Specifications www.ti.com 3 Electrical Performance Specifications 3.1 Performance Specification Summary Table 1. TPS51120 Performance Specification Summary MIN TYP MAX Input voltage range, (VVIN) SPECIFICATION TEST CONDITIONS 2.4 3.3 3.5 VDDQ voltage range (VVDDQ) 1.2 2.5 VLDOIN Voltage range (VVLDOIN) 1.2 2.5 UNIT V VTT TERMINATION VOLTAGE DDR DDR2 DDR3 LP DDR3 VTT termination voltage tolerance VTT 1.25 VTTREF 1.25 VTT 0.9 VTTREF 0.9 VTT 0.
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Electrical Performance Specifications www.ti.com Figure 1.
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Electrical Performance Specifications www.ti.com Figure 2.
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Test Setup 4 www.ti.com Test Setup This section shows the test setups used and the tests performed in evaluating the EVM. See the TPS51120 data sheet (SLUS670) for complete details regarding the operation and specifications. 4.1 4.1.1 Equipment Voltage Source Table 2. I/O and Jumper Connections JACK 4.1.2 CONNECTION VIN The input voltage source 1 should be a 0 V to 10 V variable DC source capable of supplying 1Adc. Connect Vin to J1 as shown in Figure 3.
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Test Setup www.ti.com 4.2 Recommended Test Setup DC Source 4 5VINPUT 5V V6 DC Source 3 VLDOIN 1.2V-2.5V DC Source 2 VDDQ 1.2V-2.5V DC source1 Vin 3.3V V2 V1 V3 V2 FAN V5 V4 . VTTLoad1 1.25V/0.6V 10A 20M Hz 1M W , AC Oscilloscope Figure 3.
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Test Setup 4.3 www.ti.com List of Test Points Table 3 lists the functions of each test point. Table 3. Test Points 4.4 TEST POINTS NAME DESCRIPTION TP1 VIN+ 3.3V or 2.5V input TP2 GND GND for VIN and VDDQ measurement TP3 VDDQ VDDQ input 1.2 V to 2.5 V TP4 VLDOIN VLDOIN input 1.2 V to 2.
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Test Procedure www.ti.com 4.4.3 Power Down Power off the DC sources and loads in the following order. 1. Power off DC Source 4. 2. Power off DC Source 3. 3. Power off DC Source2. 4. Power off DC Source 1. 5. Power off Load 1. 6. Power off Load 2. 5 Test Procedure 5.1 DDR Operation 5.1.1 DDR Source Load Regulation 1. Set Switch S1 to the OFF position. 2. Ensure DC Source 4 is OFF. 3. Increase VIN (DC Source 1) from 0 V to 3.3 V at J1. This is the bias supply required for TPS51200 operation.
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Test Procedure www.ti.com 9. Set Switch S1 to the OFF position. 10. Decrease DC Source 4 to 0 V. 11. Decrease DC Source 3 to 0 V. 12. Decrease DC Source 2 to 0 V. 13. Decrease DC Source 1 to 0 V. 5.2 DDR2 Operation 5.2.1 DDR2 Source Load Regulation 1. Set Switch S1 to the OFF position. 2. Ensure DC Source 4 is OFF. 3. Increase VIN (DC Source 1) from 0 V to 3.3 V at J1. This is the bias supply required for TPS51200 operation. Using V1, verify that VIN measures between 3.25 V and 3.35 V. 4.
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www.ti.com Test Procedure 5.3 DDR3 Operation 5.3.1 DDR3 Source Load Regulation 1. Set Switch S1 to the OFF position. 2. Ensure DC Source 4 is OFF. 3. Increase VIN (DC Source 1) from 0 V to 3.3 V at J1. This is the bias supply required for TPS51200 operation. Using V1, verify that VIN is between 3.25 V and 3.35 V. 4. Increase VDDQ (DC Source 2) from 0 V to 1.5 V at J2. This is the reference input. Using V2, verify that the VDDQ voltage is between 1.45 V and 1.55V. 5.
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Test Procedure www.ti.com 5.4 LP DDR3 Operation 5.4.1 LP DDR3 Source Load Regulation 1. Set Switch S1 to the OFF position. 2. Ensure that the DC Source 4 is OFF. 3. Increase VIN (DC Source 1) from 0 V to 3.3 V at J1. This is the bias supply required for TPS51200 operation. Using V1, verify that the VIN voltage is between 3.25 V and 3.35 V. 4. Increase VDDQ (DC Source 2) from 0 V to 1.2 V at J2. This is the reference input. Use V2 to verify that the VDDQ voltage is between 1.15 V and 1.25 V. 5.
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Test Procedure www.ti.com 5.5 Loop Measurement (TP10, TP11 and TP14) TPS51200EVM contains a 10-Ω series resistor in the feedback loop. The control loop measurement set up as shown in Figure 4. Figure 4. Control Loop Measurement Setup 5.5.1 Control Loop Measurement Process 1. Set up EVM as shown in Figure 4. 2. Follow test procedure at Step 1 through Step 9 of 5.1.1(DDR), 5.2.1 (DDR2), 5.3.1 (DDR3) or 5.4.1 (LP DDR3) to select the desired application and load condition. 3.
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Performance Data and Typical Characteristic Curves 6 www.ti.com Performance Data and Typical Characteristic Curves OUTPUT VOLTAGE vs OUTPUT CURRENT OUTPUT VOLTAGE vs OUTPUT CURRENT 0.758 0.79 VIN (V) 0.78 VIN = 2.5 V and VIN = 3.3 V 0.757 VVTT – Output Voltage – V VVTTREF – Output Voltage – V 3.3 2.5 0.77 0.76 0.75 0.74 0.73 0.72 0.756 0.755 0.754 0.753 0.71 0.70 –3 –2 –1 0 1 2 3 0.
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EVM Assembly www.ti.com A Test condition: VTT Sink/Source 1 A, VTT transient load regulation: 22 mV, Test point: VTT TP7 (+) and TP6 (–) A Figure 9. DDR3 VTT Sink/Source Transient Test Condition: VVIN=3.3 V, VVDDQ=VVLDOIN=1.5 V, VVTT=VVTTREF=0.75 V, IVTT=1 A Source Test Results: Phase margin: 43.8°, Gain margin: 20.19 dB, Crossover frequency: 869.75 kHz Figure 10.
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EVM Assembly www.ti.com Figure 12. Bottom Side Assembly Figure 13.
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EVM Assembly www.ti.com Figure 14.
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List of Materials 8 www.ti.com List of Materials Table 4 lists the materials required for the TPS51120EVM. Table 4.
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EVALUATION BOARD/KIT IMPORTANT NOTICE Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end-product fit for general consumer use. Persons handling the product(s) must have electronics training and observe good engineering practice standards.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.