Datasheet

www.ti.com
Design Example 7
2
3
4
5
1
9
8
7
6
10
TPS51200
REFIN
VLDOIN
VO
PGND
VOSNS
VIN
PGOOD
GND
EN
REFOUT
R3
100 kW
3.3 V
IN
PGOOD
SLP_S3
C5
0.1 mF
VTTREF
V
VLDOIN
= V
VDDQ
= 1.5 V
V
VTT
= 0.75 V
C4
1000 pF
R1
10 kW
V
VDDQ
= 1.5 V
R2
10 kW
UDG-08034
C6
4.7 mF
C8
10 mF
C7
10 mF
C3
10 mF
C2
10 mF
C1
10 mF
R4
(1)
C9
(1)
TPS51200
SLUS812 – FEBRUARY 2008
This design example describes a 3.3-V
IN
, DDR3 Configuration with LFP.
Figure 31. 3.3-V
IN
, DDR3 Configuration with LFP
Design Example 7 List of Materials
REFERENCE
DESCRIPTION SPECIFICATION PART NUMBER MANUFACTURER
DESIGNATOR
R1, R2 10 k Ω
R3 Resistor 100 k Ω
R4
(1)
C1, C2, C3 10 µ F, 6.3 V GRM21BR70J106KE76L Murata
C4 1000 pF
C5 0.1 µ F
Capacitor
C6 4.7 µ F, 6.3 V GRM21BR60J475KA11L Murata
C7, C8 10 µ F, 6.3 V GRM21BR70J106KE76L Murata
C9
(1)
(1) The values of R4 and C9 should be chosen to reduce the parasitic effect of the trace (between VO and the output MLCCs) and the
output capacitors (ESR and ESL).
28 Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): TPS51200