Datasheet

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THERMAL DESIGN
( )
DISS _ SRC VLDOIN VO O _ SRC
P V - V x I=
(2)
DISS _ SNK VO O _ SNK
P V I= ´
(3)
( )
J(max) A(max)
PKG
JA
T T
P
´
=
q
(4)
Land Pad
3 mm x 1.9 mm
Exposed Thermal
Die Pad,
2.48 mm x 1.74 mm
UDG-08018
TPS51200
SLUS812 – FEBRUARY 2008
Because the TPS51200 is a linear regulator, the VO current flows in both source and sink directions, thereby
dissipating power from the device. When the device is sourcing current, the voltage difference between VLDOIN
and VO times IO (I
IO
) current becomes the power dissipation as shown in Equation 2 .
In this case, if VLDOIN is connected to an alternative power supply lower than the VDDQ voltage, overall power
loss can be reduced. For the sink phase, VO voltage is applied across the internal LDO regulator, and the power
dissipation, P
DISS_SNK
can be calculated by Equation 3 .
Because the device does not sink and source current at the same time and the IO current may vary rapidly with
time, the actual power dissipation should be the time average of the above dissipations over the thermal
relaxation duration of the system. Another source of power consumption is the current used for the internal
current control circuitry from the VIN supply and the VLDOIN supply. This can be estimated as 5 mW or less
during normal operatiing conditions. This power must be effectively dissipated from the package.
Maximum power dissipation allowed by the package is calculated by Equation 4 .
P
PKG
= [T
J(MAX)
– T
A(MAX)
]/ θ
JA
where
• T
J(MAX)
is +125 ° C
• T
A(MAX)
is the maximum ambient temperature in the system
• θ
JA
is the thermal resistance from junction to ambient
The thermal performance of an LDO is greatly depends on the printed circuit board (PCB) layout. The TPS51200
is housed in a thermally-enhanced PowerPAD™ package that has an exposed die pad underneath the body. For
improved thermal performance, this die pad must be attached to ground via thermal land on the PCB. This
ground trace acts as a both a heatsink and heatspreader. The typical thermal resistance, θ
JA
, 52.06 ° C/W, is
achieved based on a land pattern of 3 mm × 1.9 mm with four vias (0.33-mm via diameter, the standard thermal
via size) without air flow (see Figure 9 ).
Figure 9. Recommend Land Pad Pattern for TPS51200
To further improve the thermal performance of this device, using a larger than recommended thermal land as
well as increasing the number of vias helps lower the thermal resistance from junction to thermal pad. The typical
thermal resistance from junction to thermal pad, θ
JP
, is 10.24 ° C/W (based on the recommend land pad and four
standard thermal vias).
16 Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): TPS51200