Datasheet

18
1uF
100nF
100nF
100nF
PGND PGND PGND
- 15V/10mA
D0 D1
D2
D4
100nF
VO1(5V)
VCLK
3.3V
13
TPS51125
EN0
13
TPS51125
EN0
Control
Input
Control
Input
15
GND
15
GND
(a) Control by MOSFET switch
(b) Control by Logic
TPS51125
SLUS786G –OCTOBER 2007–REVISED JUNE 2012 www.ti.com
VCLK for Charge Pump
270-kHz clock signal can be used for charge pump circuit to generate approximately 15-V dc voltage. The clock
signal becomes available when EN0 becomes higher than 2.4 V or open state. Example of control circuit is
shown in Figure 38. Note that the clock driver uses VO1 as its power supply. Regardless of enable or disable of
VCLK, power consumption of the TPS51125 is almost the same. Therefore even if VCLK is not used, one can let
EN0 pin open or supply logic ‘high’, as shown in Figure 38, and let VCLK pin open. This approach further
reduces the external part count.
Figure 38. Control Example of EN0 Master Enable
Figure 39. 15-V / 10-mA Charge Pump Configuration
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Product Folder Link(s): TPS51125