Datasheet

TPS51125

SLUS786G –OCTOBER 2007–REVISED JUNE 2012

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Out-of-Audio™ Light-Load Operation

Out-of-Audio™ (OOA) light-load mode is a unique control feature that keeps the switching frequency above

acoustic audible frequencies toward virtually no load condition while maintaining best of the art high conversion

efficiency. When the Out-of-Audio™ operation is selected, OOA control circuit monitors the states of both

MOSFET and force to change into the ‘ON’ state if both of MOSFETs are off for more than 32 μs. This means

that the top MOSFET is turned on even if the output voltage is higher than the target value so that the output

capacitor is tends to be overcharged.

The OOA control circuit detects the over-voltage condition and begins to modulate the on time to keep the output

voltage regulated. As a result, the output voltage becomes 0.5% higher than normal light-load operation.

Enable and Soft Start

EN0 is the control pin of VREG5, VREG3 and VREF regulators. Bring this node down to GND disables those

three regulators and minimize the shutdown supply current to 10 μA. Pulling this node up to 3.3 V or 5 V will turn

the three regulators on to standby mode. The two switch mode power supplies (channel-1, channel-2) become

ready to enable at this standby mode. The TPS51125 has an internal, 1.6 ms, voltage servo softstart for each

channel. When the ENTRIPx pin becomes higher than the enable threshold voltage, which is typically 430 mV,

an internal DAC begins ramping up the reference voltage to the PWM comparator. Smooth control of the output

voltage is maintained during start up. As TPS51125 shares one DAC with both channels, if ENTRIPx pin

becomes higher than the enable threshold voltage while another channel is starting up, soft start is postponed

until another channel soft start has completed. If both of ENTRIP1 and ENTRIP2 become higher than the enable

threshold voltage at a same time (within 60 μs), both channels start up at same time.

Table 3. Enabling State

EN0 ENTRIP1 ENTRIP2 VREF VREG5 VREG3 CH1 CH2 VCLK

GND Don’t Care Don’t Care Off Off Off Off Off Off

R to GND Off Off On On On Off Off Off

R to GND On Off On On On On Off Off

R to GND Off On On On On Off On Off

R to GND On On On On On On On Off

Open Off Off On On On Off Off Off

Open On Off On On On On Off On

Open Off On On On On Off On Off

Open On On On On On On On On

VREG5/VREG3 Linear Regulators

There are two sets of 100-mA standby linear regulators which outputs 5 V and 3.3 V, respectively. The VREG5

serves as the main power supply for the analog circuitry of the device and provides the current for gate drivers.

The VREG3 is intended mainly for auxiliary 3.3-V supply for the notebook system during standby mode.

Add a ceramic capacitor with a value of at least 33 μF and place it close to the VREG5 pin, and add at most 10

μF to the VREG3 pin. Total capacitance connected to the VREG3 pin should not exceed 10 μF.

Product Folder Link(s): TPS51125