Datasheet

TPS51124
SLVS616B –NOVEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com
DETAILED DESCRIPTION (continued)
LOW-SIDE DRIVER
The low-side driver is designed to drive high current low R
DS(on)
N-channel MOSFET(s). The drive capability is
represented by its internal resistances, which are 4 Ω for V5IN to DRVLx, and 1 Ω for DRVLx to PGNDx. A dead
time to prevent shoot through is internally generated between high-side MOSFET off to low-side MOSFET on,
and low-side MOSFET off to high-side MOSFET on. A 5-V bias voltage is delivered from V5IN supply. The
instantaneous drive current is supplied by an input capacitor connected between V5IN and GND. The average
drive current is equal to the gate charge at Vgs = 5 V times switching frequency. This gate drive current, as well
as the high-side gate drive current times 5 V, makes the driving power that needs to be dissipated from
TPS51124 package.
HIGH-SIDE DRIVER
The high-side driver is designed to drive high-current, low R
DS(on)
N-channel MOSFET(s). When configured as a
floating driver, 5-V bias voltage is delivered from V5IN supply. The average drive current is also calculated by the
gate charge at Vgs = 5 V times switching frequency. The instantaneous drive current is supplied by the flying
capacitor between VBSTx and LLx pins. The drive capability is represented by its internal resistances, which are
5 Ω for VBSTx to DRVHx and 1.5 Ω for DRVHx to LLx.
PWM FREQUENCY AND ADAPTIVE ON-TIME CONTROL
TPS51124 employs adaptive on-time control scheme and does not have a dedicated oscillator on board.
However, the part runs with pseudo-constant frequency by feed-forwarding the input and output voltage into the
on-time one-shot timer. The frequencies are set by TONSEL terminal connection as Table 1. The on-time is
controlled inverse proportional to the input voltage and proportional to the output voltage so that the duty ratio is
kept as VOUT/VIN technically with the same cycle time. Although the TPS51124 does not have a pin connected
to VIN, the input voltage is monitored at LLx pin during the ON state. This helps pin count reduction to make the
part compact without sacrificing its performance.
Table 1. TONSEL Connection and Switching Frequency Table
(Frequencies Are Approximate)
TONSEL CONNECTION SWITCHING FREQUENCY
CH1 CH2
GND 240 kHz 300 kHz
FLOAT (Open) 300 kHz 360 kHz
V5FILT 360 kHz 420 kHz
SOFT START
The TPS51124 has an internal, 1.2-ms, voltage servo soft start for each channel. When the ENx pin becomes
high, an internal DAC begins ramping up the reference voltage to the PWM comparator. Smooth control of the
output voltage is maintained during start-up. As TPS51124 shares one DAC with both channels, if ENx pin is set
to high while another channel is starting up, soft start is postponed until another channel soft start has
completed. If both of EN1 and EN2 are set high at a same time, both channels start up at same time.
POWER GOOD
The TPS51124 has power-good output for both switcher channels. The power-good function is activated after
soft start has finished. If the output voltage becomes within ±5% of the target value, internal comparators detect
power good state and the power good signal becomes high after a 510-ms internal delay. During start-up, this
internal delay starts after 1.7 times internal soft-start time to avoid a glitch of power-good signal. If the feedback
voltage goes outside of ±10% of the target value, the power-good signal becomes low after 10-ms internal delay.
Also note that if the feedback voltage goes +10% above target value and the power-good signal flags low, then
the loop attempts to correct the output by turning on the low-side driver (forced PWM mode). After the feedback
voltage returns to be within +5% of the target value and the power-good signal goes high, the controller returns
back to auto-skip mode.
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