Datasheet

ESR
R1
Co
+
0.758V
R2
Control
Logic
And
Driver
RL
VIN
VFB
DRVH
DRVL
PWM
Switching Modulator
Voltage Divider
Vc
Output Capacitor
Lx
I
L
I
C
I
O
−
+
ƒ
o
+
1
2p ESR Co
v
ƒ
sw
4
Vripple +
Vout
0.758
10 [mV]
TPS51124
SLVS616B –NOVEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com
APPLICATION INFORMATION
LOOP COMPENSATION AND EXTERNAL PARTS SELECTION
A buck converter system using D-CAP Mode can be simplified as shown below.
Figure 24. Simplifying the Modulator
The output voltage is compared with an internal reference voltage after divider resistors, R1 and R2. The PWM
comparator determines the timing to turn on the high-side MOSFET. The gain and speed of the comparator is
high enough to keep the voltage at the beginning of each on cycle (or the end of off cycle) substantially constant.
The DC output voltage may have line regulation due to ripple amplitude that slightly increases as the input
voltage increase.
For the loop stability, the 0-dB frequency, f
0
, defined in Equation 4 needs to be lower than 1/4 of the switching
frequency.
(4)
As f
0
is determined solely by the output capacitor’s characteristics, loop stability of D-CAP Mode is determined
by the capacitor’s chemistry. For example, specialty polymer capacitors (SP-CAP) have Co in the order of
several 100 mF and ESR in range of 10 mΩ. These make f
0
in the order of 100 kHz or less and the loop is
stable. However, ceramic capacitors have f
0
at more than 700 kHz, which is not suitable for this operational
mode.
Although D-CAP Mode provides many advantages such as ease-of-use, minimum external components
configuration, and extremely short response time, a sufficient amount of feedback signal needs to be provided by
an external circuit to reduce jitter level. This is due to not employing an error amplifier in the loop. The required
signal level is approximately 10 mV at the comparing point (VFB terminal). This gives Vripple at the output node
as shown in the following equation.
(5)
The output capacitor's ESR should meet this requirement.
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