Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - voltage regulators - DC DC switch controllers D-CAP™ VQFN 24

75kΩ

PGOOD1

EN1

PGOOD2

EN2

TPS51124RGE

(QFN24)

13 14 15 16

VBST1

DRVL1

LL1

DRVH1

VBST2

DRVH2

LL2

DRVL2

6 5 4 3 2 1

VO1

1.05V/10 A

IRF8113

IRF7821

VO2

1.5V/10 A

IRF8113

IRF7821

InputVoltage

3Vto28V

PowerPAD

6.8

V5IN

4.5Vto5.5V

VO2

VO1

VFB2

TONSEL

GND

VFB1

PGND2

TRIP2

V5FILT

V5IN

TRIP1

PGND1

Power

Good2

EN2

Power

Good1

EN1

SGND

PGNDPGND

SGND

SGND PGND

PGND

73.2kΩ

kΩ

28.7kΩ

22µF

2x330µF

1µH

10µF

0.1µF

4.7 μF

6.8kΩ

1 μF

3.3Ω

kΩ

0.1µF

10µF

1µH

2x330µF

TPS51124

www.ti.com

SLVS616B –NOVEMBER 2005–REVISED SEPTEMBER 2010

DUAL SYNCHRONOUS STEP-DOWN CONTROLLER FOR

LOW VOLTAGE POWER RAILS

Check for Samples: TPS51124

FEATURES

DESCRIPTION

• High Efficiency, Low-Power Consumption,

Shutdowns to <1 mA

The TPS51124 is a dual, adaptive on-time D-CAP™

mode synchronous buck controller. The part enables

• Fixed Frequency Emulated On-Time Control,

system designers to cost effectively complete the

Frequency Selectable From Three Options

suite of notebook power bus regulators with the

• D-CAP™ Mode Enables Fast Transient

absolute lowest external component count and lowest

Response

standby consumption. The fixed frequency emulated

• Auto-Skip Mode

adaptive on-time control supports seamless operation

between PWM mode at heavy load condition and

• Less Than 1% Initial Reference Accuracy

reduced frequency operation at light load for high

• Low Output Ripple

efficiency down to milliampere range. The main

• Wide Input Voltage Range: 3 V to 28 V

control loop for the TPS51124 uses the D-CAP mode

that optimized for low ESR output capacitors such as

• Output Voltage Range: 0.76 V to 5.5 V

POSCAP or SP-CAP promises fast transient

• Low-Side R

DS(ON)

Loss-less Current Sensing

response with no external compensation. Simple and

• Adaptive Gate Drivers With Integrated Boost

separate power good signals for each channel allow

Diode

flexibility of power sequencing. The part provides a

convenient and efficient operation with supply input

• Internal 1.2-ms Voltage-Servo Soft Start

voltages (V5IN, V5FILT) ranging from 4.5 V to 5.5 V,

• Power-Good Signals for Each Channel With

conversion voltages (drain voltage for the

Delay Timer

synchronous high-side MOSFET) from 3 V to 28 V

• Output Discharge During Disable, Fault

and output voltages from 0.76 V to 5.5 V.

The TPS51124 is available in 24-pin QFN package

APPLICATIONS

specified from –40°C to 85°C ambient temperature

• Notebook I/O and Low Voltage System Bus

range.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2D-CAP, PowerPAD are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (27 pages)

PAGE 1
TPS51124 www.ti.
PAGE 2
TPS51124 SLVS616B – NOVEMBER 2005 – REVISED SEPTEMBER 2010 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
PAGE 3
TPS51124 www.ti.com SLVS616B – NOVEMBER 2005 – REVISED SEPTEMBER 2010 ELECTRICAL CHARACTERISTICS over operating free-air temperature range, V5IN = V5FILT = 5 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 350 700 mA SUPPLY CURRENT IV5FILT V5FILT supply current V5FILT current, no load, EN1 = EN2 = 5 V, VFB1 = VFB2 = 0.77 V, LL1=LL2=0.
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TPS51124 SLVS616B – NOVEMBER 2005 – REVISED SEPTEMBER 2010 www.ti.com ELECTRICAL CHARACTERISTICS (Continued) over operating free-air temperature range, V5IN = V5FILT = 5 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Wake up 3.7 4.0 4.3 V Hysteresis 0.2 0.3 0.4 V Wake up 1.0 1.3 1.5 V UVLO/LOGIC THRESHOLD VUV5VFILT VEN V5FILT UVLO threshold ENx threshold IEN ENx input current Hysteresis Absolute value 0.2 (1) 0.
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TPS51124 www.ti.com SLVS616B – NOVEMBER 2005 – REVISED SEPTEMBER 2010 DEVICE INFORMATION PIN FUNCTIONS PIN NAME NO. DRVH1 21 DRVH2 10 DRVL1 19 DRVL2 12 EN1 23 EN2 8 GND 3 LL1 20 LL2 11 PGND1 18 PGND2 13 PGOOD1 24 PGOOD2 7 TONSEL 4 TRIP1 17 TRIP2 14 VBST1 22 I/O DESCRIPTION O Synchronous high-side MOSFET driver outputs. LL node referenced floating drivers. The gate drive voltage is defined by the voltage across VBST to LL node flying capacitor.
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TPS51124 SLVS616B – NOVEMBER 2005 – REVISED SEPTEMBER 2010 www.ti.com FUNCTIONAL BLOCK DIAGRAM V5IN Frequency Control 160 °C/ 150 °C 4V FAST MID 4 V/3.
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TPS51124 www.ti.com SLVS616B – NOVEMBER 2005 – REVISED SEPTEMBER 2010 DETAILED DESCRIPTION PWM OPERATION The main control loop of the switching mode power supply (SMPS) is designed as an adaptive on-time pulse width modulation (PWM) controller. It supports a proprietary D-CAP Mode. D-CAP Mode uses an internal compensation circuit and is suitable for low external component-count configuration, with appropriate amount of ESR at the output capacitor(s).
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TPS51124 SLVS616B – NOVEMBER 2005 – REVISED SEPTEMBER 2010 www.ti.com DETAILED DESCRIPTION (continued) LOW-SIDE DRIVER The low-side driver is designed to drive high current low RDS(on) N-channel MOSFET(s). The drive capability is represented by its internal resistances, which are 4 Ω for V5IN to DRVLx, and 1 Ω for DRVLx to PGNDx. A dead time to prevent shoot through is internally generated between high-side MOSFET off to low-side MOSFET on, and low-side MOSFET off to high-side MOSFET on.
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TPS51124 www.ti.com SLVS616B – NOVEMBER 2005 – REVISED SEPTEMBER 2010 DETAILED DESCRIPTION (continued) OUTPUT DISCHARGE CONTROL TPS51124 discharges the output when ENx is low, or the controller is turned off by the protection functions (OVP, UVP, UVLO, and thermal shutdown). TPS51124 discharges outputs using an internal, 10-Ω MOSFET which is connected to VOx and PGNDx.
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TPS51124 SLVS616B – NOVEMBER 2005 – REVISED SEPTEMBER 2010 www.ti.com TYPICAL CHARACTERISTICS V5FILT SUPPLY CURRENT vs JUNCTION TEMPERATURE V5FILT SHUTDOWN CURRENT vs JUNCTION TEMPERATURE 1 I V5FLTSDN − Shutdown Current − µ A I V5FILT − Supply Current − µ A 500 400 300 200 100 0 −50 0 50 100 TJ − Junction Temperature − 5C 0.8 0.6 0.4 0.2 0 −50 150 0 50 100 TJ − Junction Temperature − 5C Figure 1. Figure 2.
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TPS51124 www.ti.com SLVS616B – NOVEMBER 2005 – REVISED SEPTEMBER 2010 TYPICAL CHARACTERISTICS (continued) OVP/UVP THRESHOLD vs JUNCTION TEMPERATURE SWITCHING FREQUENCY (SLOW) vs INPUT VOLTAGE 500 140 fSW − Switching Frequency − kHz VOVP VUVP − OVP/UVP Threshold − % TONSEL = GND 120 OVP 100 80 UVP 60 40 −50 400 CH1 200 100 0 0 50 100 TJ − Junction Temperature − 5C CH2 300 150 0 5 Figure 6.
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TPS51124 SLVS616B – NOVEMBER 2005 – REVISED SEPTEMBER 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) SWITCHING FREQUENCY (SLOW) vs OUTPUT CURRENT SWITCHING FREQUENCY (MED) vs OUTPUT CURRENT 500 500 TONSEL = FLOAT fSW − Switching Frequency − kHz fSW − Switching Frequency − kHz TONSEL = GND 400 CH2 300 200 CH1 100 0 0.001 0.01 0.1 1 400 CH2 300 CH1 200 100 0 0.001 10 0.01 0.1 1 IO − Output Current − A IO − Output Current − A Figure 9. Figure 10.
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TPS51124 www.ti.com SLVS616B – NOVEMBER 2005 – REVISED SEPTEMBER 2010 TYPICAL CHARACTERISTICS (continued) 1.5-V OUTPUT VOLTAGE vs OUTPUT CURRENT 1.05-V OUTPUT VOLTAGE vs INPUT VOLTAGE 1.1 1.575 1.05 V TONSEL = FLOAT 1.5 V TONSEL = FLOAT VOUT1 − Output Voltage − V VOUT2 − Output Voltage − V 1.550 VI = 21 V 1.525 1.500 VI = 7 V VI = 12 V 1.475 1.075 IO = 0 A 1.050 IO = 5 A 1.025 1.450 1.425 0.001 1 0.01 0.1 1 IOUT2 − Output Current − A Figure 13. 0 10 20 25 Figure 14. 1.
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TPS51124 SLVS616B – NOVEMBER 2005 – REVISED SEPTEMBER 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) 1.5-V EFFICIENCY vs OUTPUT CURRENT 100 VI = 7 V 1.5 V TONSEL = FLOAT TONSEL = FLOAT 80 VI = 21 V − Efficiency − % 1.05-V LOAD TRANSIENT RESPONSE VOUT1 (50 mV/div) VI = 12 V 60 IIND1 (5 A/div) 40 20 0 0.001 IOUT1 (5 A/div) 0.01 0.1 1 IOUT2 − Output Current − A Figure 17. 10 t − Time − 20 ms/div Figure 18. (4) 1.5-V LOAD TRANSIENT RESPONSE TONSEL = FLOAT 1.
PAGE 15
TPS51124 www.ti.com SLVS616B – NOVEMBER 2005 – REVISED SEPTEMBER 2010 TYPICAL CHARACTERISTICS (continued) 1.5-V START-UP WAVEFORMS 1.05-V DISCHARGE WAVEFORMS EN2 (5 V/div) EN1 (5 V/div) VO2 (0.5 V/div) VO1 (1 V/div) PGOOD1 (5 V/div) PGOOD2 (5 V/div) DRVL1 (5 V/div) t − Time − 500 ms/div Figure 21. t − Time −1 ms/div Figure 22. (5) 1.5-V DISCHARGE WAVEFORMS EN2 (5 V/div) VO2 (1 V/div) PGOOD2 (5 V/div) DRVL2 (5 V/div) t − Time − 1 ms/div Figure 23.
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TPS51124 SLVS616B – NOVEMBER 2005 – REVISED SEPTEMBER 2010 www.ti.com APPLICATION INFORMATION LOOP COMPENSATION AND EXTERNAL PARTS SELECTION A buck converter system using D-CAP Mode can be simplified as shown below. VIN R1 DRVH PWM VFB − + R2 + Control Logic And Driver Lx IL 0.758V Voltage Divider IC DRVL IO ESR Vc Switching Modulator RL Co Output Capacitor Figure 24.
PAGE 17
TPS51124 www.ti.com SLVS616B – NOVEMBER 2005 – REVISED SEPTEMBER 2010 The external components selection is much simpler in D-CAP Mode. 1. Determine the value of R1 and R2. Recommended R2 value is from 10 kΩ to 100 kΩ. Determine R1 using the following equation. R1 + ǒV out * 0.758Ǔ 0.758 2. Choose inductor. R2 (6) The inductance value should be determined to give the ripple current of approximately 1/4 to 1/2 of maximum output current.
PAGE 18
TPS51124 SLVS616B – NOVEMBER 2005 – REVISED SEPTEMBER 2010 www.ti.com Input Voltage 3 V to 28 V EN2 C5 0.1 µF GND VFB1 TONSEL 9 VBST2 1 EN1 23 TPS51124RGE (QFN24) VBST1 22 EN1 13 16 17 R7 R3 3.3Ω 6.8 kΩ R6 6.8 kΩ C7 4.7 μF PGND PGND1 15 V5IN 14 Q1 IRF7821 C2 0.1 µF DRVH1 21 LL1 20 12 DRVL2 PGND Power Good1 PGOOD1 24 11 LL2 C4 2 x 330 µF 4.5 V to 5.5 V 2 PowerPAD 8 EN2 10 DRVH2 Q4 IRF8113 V5IN 3 TRIP1 L2 1 µH R1 28.7 kΩ TM V5FILT 10 µF 7 PGOOD2 TRIP2 VO2 1.
PAGE 19
TPS51124 www.ti.com SLVS616B – NOVEMBER 2005 – REVISED SEPTEMBER 2010 REVISION HISTORY Changes from Original (November 2005) to Revision A Page • Updated the the circut illustration, Pin 21 changed From DRVL1 To: DRVH1 and Pin 19 changed From: DRVH1 to DRVL1 ..................................................................................................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 15-Apr-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS51124RGER VQFN RGE 24 3000 330.0 12.4 4.3 4.3 1.1 8.0 12.0 Q2 TPS51124RGET VQFN RGE 24 250 180.0 12.4 4.3 4.3 1.1 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 15-Apr-2014 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS51124RGER VQFN RGE 24 3000 370.0 355.0 55.0 TPS51124RGET VQFN RGE 24 250 195.0 200.0 45.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.