Datasheet

TPS51123A
www.ti.com SLUSAA6C –APRIL 2011–REVISED SEPTEMBER 2012
Layout Considerations
Certain points must be considered before starting a layout work using the TPS51123A.
• TPS51123A has only one GND pin and special care of GND trace design makes operation stable, especially
when both channels operate. Group GND terminals of output voltage divider of both channels and the VREF
capacitor as close as possible, and connect them to an inner GND plane with PowerPad and the overcurrent
setting resistor, as shown in the thin GND line of Figure 37. This trace is named Signal Ground (SGND).
Group ground terminals of VIN capacitor(s), VOUT capacitor(s) and source of low-side MOSFETs as close as
possible, and connect them to another inner GND plane with GND pin of the device and the GND terminal of
VREG3 and VREG5 capacitors, as shown in the bold GND line of Figure 37. This trace is named Power
Ground (PGND). SGND should be connected to PGND at the middle point between ground terminal of V
OUT
capacitors.
• Inductor, V
OUT
capacitor(s), V
IN
capacitor(s) and MOSFETs are the power components and should be placed
on one side of the PCB (solder side). Power components of each channel should be at the same distance
from the TPS51123A. Other small signal parts should be placed on another side (component side). Inner
GND planes should shield and isolate the small signal traces from noisy power lines.
• PCB trace defined as LLx node, which connects to source of high-side MOSFET, drain of low-side MOSFET
and high-voltage side of the inductor, should be as short and wide as possible.
• A high-quality X5R or X7R ceramic bypass capacitor should be placed close to the device and traces should
be no longer than 10 mm. Use the following capacitance values.
– VREG5: 10 µF or larger
– VREG3: 10 µF or larger (1 µF is acceptable when not loaded)
– VREF: between 220 nF and 1 µF
• Connect the overcurrent setting resistors from TRIPx to SGND and close to the device, right next to the
device if possible.
• The discharge path (VOx) should have a dedicated trace to the output capacitor; separate from the output
voltage sensing trace. When LDO5 is switched over Vo1 trace should be 1.5 mm with no loops. When LDO3
is switched over and loaded VO2 trace should also be 1.5 mm with no loops. There is no restriction for just
monitoring Vox. Make the feedback current setting resistor (the resistor between VFBx to SGND) close to the
device. Place on the component side and avoid vias between this resistor and the device.
• Connections from the drivers to the respective gate of the high-side or the low-side MOSFET should be as
short as possible to reduce stray inductance. Use 0.65-mm (25 mils) or wider trace and via(s) of at least 0.5
mm (20 mils) diameter along this trace.
• All sensitive analog traces and components such as VOx, VFBx, VREF, GND, EN0, TRIPx, PGOOD,
TONSEL and SKIPSEL should be placed away from high-voltage switching nodes such as LLx, DRVLx, and
DRVHx nodes to avoid coupling.
• Traces for VFB1 and VFB2 should be short and laid apart each other to avoid channel to channel
interference.
• In order to effectively remove heat from the package, prepare thermal land and solder to the package’s
thermal pad. Three by three or more vias with a 0.33-mm (13 mils) diameter connected from the thermal land
to the internal ground plane should be used to help dissipation. This thermal land underneath the package
should be connected to SGND, and should NOT be connected to PGND.
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