Datasheet

TPS51123A
www.ti.com SLUSAA6C –APRIL 2011–REVISED SEPTEMBER 2012
Enable and Soft Start
EN0 is the control pin of VREG5, VREG3 and VREF regulators. Bring this node down to GND disables those
three regulators and minimize the shutdown supply current to 10 μA. Pulling this node up to 3.3 V or 5 V will turn
the three regulators on to standby mode. The two switch mode power supplies (channel-1, channel-2) become
ready to enable at this standby mode. The TPS51123A has an internal, 1.6 ms, voltage servo soft-start for each
channel.
Both channel 1 and channel 2 can be enabled simultaneously with the ENC pin when only the OCL trip setting
resistance is connected to TRIPx pin. Channel 1 and channel 2 can be disabled independently by shorting the
TRIPx pin to ground when the ENC pin voltage is higher than its enable threshold, which is typically 1.26 V. After
enabling channel 1 and/or channel 2, an internal DAC begins ramping up the reference voltage of the PWM
comparator. Smooth control of the output voltage is maintained during start up. As TPS51123A shares one DAC
with both channels, if TRIPx pin becomes higher than the enable threshold voltage while another channel is
starting up, soft-start is postponed until another channel soft-start has completed. If both of TRIP1 and TRIP2
become higher than the enable threshold voltage at the same time (within 60 µs), both channels start up
simultaneously.
Table 4. Enabling State
EN0 ENC TRIP1 TRIP2 VREF VREG5 VREG3 CH1 CH2
GND No effect
(1)
No effect
(1)
No effect
(1)
Off Off Off Off Off
Open Low No effect
(1)
No effect
(1)
On On On Off Off
Open High Low Low On On On Off Off
Open High High Low On On On On Off
Open High Low High On On On Off On
Open High High High On On On On On
(1) Either high or low, does no affect the enable state.
VREG5/VREG3 Linear Regulators
There are two sets of 100-mA standby linear regulators which outputs 5 V and 3.3 V, respectively. The VREG5
serves as the main power supply for the analog circuitry of the device and provides the current for gate drivers.
The VREG3 is intended mainly for auxiliary 3.3-V supply for the notebook system during standby mode.
Add a high-quality X5R or X7R ceramic capacitor with a value of 10-µF or larger placed close to the VREG5 and
VREG3 pins to stabilize LDOs. For VREG3, a 1-µF ceramic capacitor is acceptable when not loaded.
VREG5 Switch Over
When the VO1 voltage becomes higher than 4.7 V AND channel-1 internal powergood flag is generated, internal
5-V LDO regulator is shut off and the VREG5 output is connected to VO1 by internal switch over MOSFET. The
510-μs powergood delay helps a switch over without glitch.
VREG3 Switch Over
When the VO2 voltage becomes higher than 3.15 V AND channel-2 internal powergood flag is generated,
internal 3.3-V LDO regulator is shut off and the VREG3 output is connected to VO2 by internal switch over
MOSFET. The 510-μs powergood delay helps a switch over without glitch.
Powergood
The TPS51123A has one powergood output that indicates a high state when both switcher outputs are within the
targets (AND gated). The powergood function is activated with 2-ms internal delay after ENC goes high. If the
output voltage becomes within ±5% of the target value, internal comparators detect power good state and the
powergood signal becomes high after 510-μs internal delay. Therefore PGOOD goes high around 2.5 ms after
ENC goes high. If the output voltage goes outside of ±10% of the target value, the powergood signal becomes
low after 2-μs internal delay. The powergood output is an open drain output and is needed to be pulled up
outside.
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