Datasheet

2 ESR C 4

= £

p ´ ´

ESR

Control

logic

Driver

VIN

VFB

DRVH

DRVL

PWM

Switching ModulatorVoltage Divider

IoIc

Output Capacitor

TPS51123A

www.ti.com

SLUSAA6C –APRIL 2011–REVISED SEPTEMBER 2012

Loop Compensation

From small-signal loop analysis, a buck converter using D-CAP

mode can be simplified as below.

Figure 36. Simplifying the Modulator

The output voltage is compared with internal reference voltage after divider resistors, R1 and R2. The PWM

comparator determines the timing to turn on high-side MOSFET. The gain and speed of the comparator is high

enough to keep the voltage at the beginning of each on cycle substantially constant. For the loop stability, the

0dB frequency, f

, defined below need to be lower than 1/4 of the switching frequency.

(1)

As f

is determined solely by the output capacitor's characteristics, loop stability of D-CAP

mode is determined

by the capacitor's chemistry. For example, specialty polymer capacitors (SP-CAP) have Co in the order of

several 100 μF and ESR in range of 10 mΩ. These make f

on the order of 100 kHz or less and the loop will be

stable. However, ceramic capacitors have f

at more than 700 kHz, which is not suitable for this operational

mode.

Ramp Signal

The TPS51123A adds a ramp signal to the 2-V reference in order to improve its jitter performance. As described

in the previous section, the feedback voltage is compared with the reference information to keep the output

voltage in regulation. By adding a small ramp signal to the reference, the dignal-to-noise ratio at the onset of a

new switching cycle is improved. Therefore the operation becomes less jitter and stable. The ramp signal is

controlled to start with -20 mV at the beginning of ON-cycle and to become 0 mV at the end of OFF-cycle in

steady state. By using this scheme, the TPS51123A improve jitter performance without sacrificing the reference

accuracy.

Product Folder Links: TPS51123A