Datasheet

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Layout Considerations
9
10
11
12
32
31
30
29
SKIPSEL
TONSEL
PGOOD1
EN1
EN5
EN3
PGOOD2
EN2
TPS51120RHB
(QFN−32)
13
14
15
16
28
27
26
25
VBST1
DRVH1
LL1
DRVL1
VBST2
DRVH2
LL2
DRVL2
17
PGND2
8
VO2
7
COMP2
6
VFB2
5
GND
4
VREF2
3
VFB1
2
COMP1
1
VO1
18
CS2
19
VREG3
20
V5FILT
21
V5REG
22
VIN
23
CS1
24
PGND1
C30
NA
+
VO1
5V/6A
Q2
IRF7832
Q1
IRF7821
−
VO1_GND
PGND1
VBAT
+
VO2
3.3V/6A
Q4
IRF7832
Q3
IRF7821
−VO2_GND
PGND2
VBAT
VBAT
GND
PowerPAD
R50
5.1
W
V5FILT
EN_1
P_GOOD1
P_GOOD2
EN_2
EN_LDO5
EN_LDO3
GND
R11
100 kΩ
C10
20 µF
L1
4.7 µH
C1B
150 µF
C1A
150 µF
C11
0.1 µF
C31
1 nF
R21
100 kΩ
C21
0.1 µF
C10
20 µF
L2
2.2 µH
C2A
150 µF
C2B
150 µF
R22
3.3 kΩ
R12
3.6 kΩ
C51
1 µF
C50
10 µF
C30
10 µF
UDG−05074
TPS51120
SLUS670B – JULY 2005 – REVISED FEBRUARY 2007
Certain points must be considered before starting a layout work using the TPS51120.
• Connect RC low-pass filter from VREG5 to V5FILT, 1 µ F and 5.1 Ω are recommended. Place the filter
capacitor close to the device, within 12 mm (0.5 inches) if possible.
• VREG5 and VREG3 require at least 4.7 µ F, VREF2 requires a 1-nF ceramic bypass capacitor which should
be placed close to the device and traces should be no longer than 10 mm.
• Connect the overcurrent setting resistors from CSx to V5FILT (NOT VREG5) and close to the device, right
next to the device if possible. The trace from CSx to V5FILT should avoid coupling to high-voltage switching
node.
• In the case of using adjustable output voltage with an external resistor divider, the discharge path (VOx)
should have a dedicated trace to the output capacitor; separate from the output voltage sensing trace, and
use 1.5 mm or wider trace with no loops. Make the feedback current setting resistor (the resistor between
VFBx to GND) is tied close to the device’s GND. Place on the component side and avoid vias between this
resistor and the device.
• Connections from the drivers to the respective gate of the high-side or the low-side MOSFET should be as
short as possible to reduce stray inductance. Use 0.65 mm (25 mils) or wider trace.
• All sensitive analog traces and components such as VOx, COMPx, VFBx, VREF2, GND, ENx, PGOODx,
CSx, V5FILT, TONSEL and SKIPSEL should be placed away from high-voltage switching nodes such as
LLx, DRVLx or DRVHx nodes to avoid coupling. Use internal layer(s) as ground plane(s) and shield feedback
trace from power traces and components.
• Gather ground terminal of VIN capacitor(s), V
OUT
capacitor(s) and source of low-side MOSFETs as close as
possible. GND (signal ground) and PGNDx (power ground) should be connected strongly together near the
device. PCB trace defined as LLx node, which connects to source of high-side MOSFET, drain of low-side
MOSFET and high-voltage side of the inductor, should be as short and wide as possible.
• In order to effectively remove heat from the package, prepare thermal land and solder to the package’s
thermal pad. Three by three or more vias with a 0.33-mm (13mils) diameter connected from the thermal land
to the internal ground plane should be used to help dissipation. Do NOT connect PGNDx to this thermal land
underneath the package.
Figure 3. D-CAP™ Mode, Fixed 5-V/6-A, +3.3-V/6-A, R
DS(on)
Sensing
22
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