Datasheet

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3.3V, 100 mA, LDO and Switchover (VREG3)
2V, 50 µ A Sink/Source Reference (VREF2)
Low-Side Driver
High-Side Driver
Soft-Start
TPS51120
SLUS670B – JULY 2005 – REVISED FEBRUARY 2007
DETAILED DESCRIPTION (continued)
A 3.3-V, 100-mA linear regulator is integrated as a second regulator in the TPS51120. This LDO provides a
handy standby supply for 3.3 V ‘Always On’ voltages in the notebook system. The characteristics of this LDO are
identical to the 5V LDO except for the switchover voltage. Apply 10- µ F ceramic capacitor from VREG3 to PGND
in adjacent to the device. If the VO2 voltage exceeds 3.1 V, then this regulator is switched off and the 3.3 V rail
is bootstrapped to the 3.3 V switcher. Note if the VO2 voltage is set higher by external feedback dividers, for
example 5 V, that high voltage is presented at VREG3 after switchover. The EN3 pin is a low voltage input that
can be tied to V5FILT or left open to enable the 3.3-V regulator. This 3.3-V regulator can be turned on or kept
alive independent to the 5-V regulator.
This is a handy reference for generating auxiliary voltages. The tolerance is ± 2% over 50- µ A load and 0 ° C to
85 ° C ambient temperature ranges. The four-state logic (SKIPSEL, TONSEL) takes advantage of this reference
for additional selection modes. This reference is enabled when both EN3 and EN5 become high, shuts down
after both switchers are turned off and VREG5 or VREG3 is shut down. Please refer to Table 4 . If this output is
forcibly tied down to ground, both SMPS are turned off without latch. Bypass VREF2 pin to GND by a 1-nF
capacitor.
The low-side gate driver, DRVL, is designed to drive high current low R
DS(on)
N-channel MOSFET(s). The
maximum drive voltage is 5.5 V which is delivered from VREF5 pin. The instantaneous drive current is supplied
from the output capacitor at the VREF5 pin. The average drive current is equal to the FET’s gate charge at
VGS=5 V times switching frequency. The VREG5 pin voltage may contain high frequency noise due to parasitic
inductance by wiring and pointing current flow into the gate capacitor. The drive capability is represented by its
internal resistance, which are 3.5 Ω for VREG5 to DRVL and 1.5 Ω for DRVL to PGND. Adaptive dead time
control generates delay times between top MOSFET off to bottom MOSFET on, and bottom MOSFET off to top
MOSFET on, preventing the totem-pole switches to shoot through. Top MOSFET off is detected as LL-node
voltage declining below 2 V. Bottom MOSFET off is detected as DRVL voltage become 1.1 V.
The high-side gate driver, DRVH, is designed to drive high current, low R
DS(on)
N-channel MOSFET(s). When
configured as a LL-node referenced floating driver, connect 0.1- µ F ceramic capacitor between corresponding
VBST pin and LL pin. A 5-V bias voltage is delivered from VREG5 supply. VBST is internally connected to
VREG5 through a high voltage PN diode. This internal diode provides sufficient gate voltage for ordinary 4.5-V
drive power MOSFETs and helps reducing external component. However, in the case where the gate bias
voltage is critical for driving the top MOSFET, application designer may add an external schottky diode from
VREG5 pin to VBST pin. Note schottky diodes have quite high reverse leakage current at high temperature. The
instantaneous drive current is supplied by the flying capacitor connected between VBST and LL pins. The
average drive current is equal to the gate charge at VGS=5 V times switching frequency. The drive capability is
represented by its internal resistance, which are 3.5- Ω for VBST to DRVH and 1.5 Ω for DRVH to LL. The
maximum recommended voltage that can be applied between DRVH pin and LL pin is 5.5 V, DRVH pin to
PGND pin is 34 V.
The TPS51120 has an internal 3-ms voltage-servo soft start for each channel. When the EN1 or EN2 pin
exceeds 0.9 V, an internal DAC begins ramping up the reference voltage. Smooth control of the output voltage
during start up is maintained. However, if a slower soft-start is required, an external capacitor may be tied from
the EN1 or EN2 pin to GND. In this case, the TPS51120 charges the external capacitor with the integrated 2- µ A
current source. The lower of either the EN voltage slew rate or the internal soft start slew rate dominates the
start-up ramp. In addition, if tracking discharge is required, the EN pin can be used to control the output voltage
discharge smoothly. An approximate value for the soft start reference voltage as a function of EN voltage is
V
SSREF
= (V
ENX
– 0.9)/1.5 < 1 V. At the beginning of soft-start period, the rectifying MOSFET maintains an off
state until the top MOSFET is turned on for at least once. This prevents high negative current to flow back from
the output capacitor in the event of output capacitor pre-charged condition.
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