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Light Load Operation
I
OUT(LL)
+
1
2 L f
ǒ
V
IN
* V
OUT
Ǔ
V
OUT
V
IN
(1)
Forced PWM Operation
5V, 100 mA, LDO and Switchover (VREG5)
TPS51120
SLUS670B – JULY 2005 – REVISED FEBRUARY 2007
DETAILED DESCRIPTION (continued)
TPS51120 automatically reduces switching frequency at light load condition to maintain high efficiency. This
reduction of frequency is achieved smoothly and without an increase in load regulation. Detail operation is
described as follows. As the output current decreases from heavy load condition, the inductor current is also
reduced and eventually comes to the point that its ‘valley’ touches zero current, which is the boundary between
continuous conduction and discontinuous conduction modes. The rectifying MOSFET is turned off when this
zero inductor current is detected. The on-time is kept the same as that in the heavy load condition. As the load
current further decreases, the converter runs in discontinuous conduction mode and it takes longer and longer to
discharge the output capacitor to the level that requires next ‘ON’ cycle. This results in reducing the switching
frequency. In reverse, when the output current increases from light load to heavy load, switching frequency
increases to the constant predetermined frequency as the inductor current reaches to the continuous
conduction. The transition load point to the light load operation I
OUT(LL)
(i.e. the threshold between continuous
and discontinuous conduction mode) can be calculated as shown in Equation 1 .
where f is the PWM switching frequency which is determined by TONSEL pin. Switching frequency versus
output current in the light load condition is a function of L, f, V
IN
and V
OUT
, but it decreases almost proportional to
the output current from the I
OUT(LL)
given in Equation 1 .
Tying SKIPSEL to V5FILT or leaving it float force the part to operate in continuous conduction mode for entire
load range by disabling zero inductor current detection. Switching frequency is kept at the frequency selected by
TONSEL input. System designers may want to use this mode to avoid certain frequency in light load condition
with the cost of low efficiency. However, please be aware the output has a capability to both sink and source
current in this mode. If the output terminal is connected to a voltage source higher than the regulated voltage,
the converter sinks current from the output and boosts the charge into the input capacitor. This may cause
unexpected high voltage at VIN and may damage the part.
A 5-V, 100-mA linear regulator is integrated in the TPS51120. This low drop-out (LDO) regulator services the
main analog supply rail for the IC and provides the current for the gate drivers. The regulator is a PMOS type
with transconductance control and the pole is determined by the value of output capacitance. Typically, the
value of this capacitor must be greater than 4.7 µ F. A 10- µ F ceramic capacitor is recommended for a typical
design. Current limit and thermal protection are included in the regulator. Additionally, if the VO1 voltage
exceeds 4.8 V, then the regulator is switched off and the 5V rails are bootstrapped to the 5-V switcher output,
improving the efficiency of the converter. A glitch-free switchover is accomplished. The VREG5 output voltage
does not show a short “glitch” down to 4.8 V when this bootstrapping action is taken. The switchover impedance
from VO1 to VREG5 is typically 1.3 Ω . Standby current is designed for 30- µ A operation allowing the user to
leave the regulator alive while maintaining maximum battery life. The EN5 pin is a high voltage input and can be
tied to VBAT or left open to enable the 5-V regulator. This 5-V regulator must be enabled prior to enable
switching regulators. Pull EN5 to ground to shut off the regulator. Disabling the regulator does not promise
shutting down the switchers once 5 volts is supplied via the bootstrap path. Because switchover occurs, the 5-V
switcher MUST be turned off with the LDO in order to shut down the device. EN5 does NOT function as a
master disable.
13
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