Datasheet
Table Of Contents
- FEATURES
- DESCRIPTION
- APPLICATIONS
- ABSOLUTE MAXIMUM RATINGS
- DISSIPATION RATINGS
- RECOMMENDED OPERATING CONDITIONS
- ELECTRICAL CHARACTERISTICS
- DEVICE INFORMATION
- DETAILED DESCRIPTION
- VDDQ SMPS, Dual PWM Operation Modes
- VDDQ SMPS, Light Load Condition
- Low-Side Driver
- High-Side Driver
- Current Sensing Scheme
- PWM Frequency and Adaptive On-Time Control
- VDDQ Output Voltage Selection
- VTT Linear Regulator and VTTREF
- Controling Outputs Using the S3 and S5 Pins
- Soft-Start and Powergood
- VDDQ and VTT Discharge Control
- Current Protection for VDDQ
- Current Protection for VTT
- Overvoltage and Undervoltage Protection for VDDQ
- V5IN (PWP), V5FILT (RGE) Undervoltage Lockout (UVLO) Protection
- V5IN (PWP), V5FILT (RGE) Input Capacitor
- Thermal Shutdown
- APPLICATION INFORMATION
- TYPICAL CHARACTERISTICS
TI Information — Selective Disclosure
TPS51116
SLUS609I –MAY 2004–REVISED JANUARY 2014
www.ti.com
DEVICE INFORMATION
TERMINAL FUNCTIONS
TERMINAL
NO. I/O DESCRIPTION
NAME
PWP RGE
Output of the transconductance amplifier for phase compensation. Connect to V5IN to disable
COMP 8 6 I/O
gm amplifier and use D-CAP™ mode.
Current sense comparator input (-) for resistor current sense scheme. Or overcurrent trip
CS 15 16 I/O voltage setting input for R
DS(on)
current sense scheme if connected to V5IN (PWP), V5FILT
(RGE) through the voltage setting resistor.
DRVH 19 21 O Switching (top) MOSFET gate drive output.
DRVL 17 19 O Rectifying (bottom) MOSFET gate drive output.
GND 5 3 - Signal ground. Connect to minus terminal of the VTT LDO output capacitor.
CS_GND - 17 – Current sense comparator input (+) and ground for powergood circuit.
Switching (top) MOSFET gate driver return. Current sense comparator input (-) for R
DS(on)
LL 18 20 I/O
current sense.
MODE 6 4 I Discharge mode setting pin. See VDDQ and VTT Discharge Control section.
– 7 –
NC No connect.
– 12 –
Ground for rectifying (bottom) MOSFET gate driver (PWP, RGE). Also current sense
PGND 16 18 –
comparator input(+) and ground for powergood circuit (PWP).
Powergood signal open drain output, In HIGH state when VDDQ output voltage is within the
PGOOD 13 13 O
target range.
S3 11 10 I S3 signal input.
S5 12 11 I S5 signal input.
V5IN 14 15 I 5-V power supply input for internal circuits (PWP) and MOSFET gate drivers (PWP, RGE).
Filtered 5-V power supply input for internal circuits. Connect R-C network from V5IN to
V5FILT - 14 I
V5FILT.
VBST 20 22 I/O Switching (top) MOSFET driver bootstrap voltage input.
VDDQSET 10 9 I VDDQ output voltage setting pin. See VDDQ Output Voltage Selection section.
VDDQ reference input for VTT and VTTREF. Power supply for the VTTREF. Discharge
VDDQSNS 9 8 I/O current sinking terminal for VDDQ Non-tracking discharge. Output voltage feedback input for
VDDQ output if VDDQSET pin is connected to V5IN or GND.
VLDOIN 1 23 I Power supply for the VTT LDO.
VTT 2 24 O Power output for the VTT LDO.
VTTGND 3 1 - Power ground output for the VTT LDO.
VTTREF 7 5 O VTTREF buffered reference output.
Voltage sense input for the VTT LDO. Connect to plus terminal of the VTT LDO output
VTTSNS 4 2 I
capacitor.
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