Datasheet

PWM Frequency and Adaptive On-Time Control
VDDQ Output Voltage Selection
VTT Linear Regulator and VTTREF
Outputs Management by S3, S5 Control
TPS51116
SLUS609H – MAY 2004 – REVISED JULY 2009 ................................................................................................................................................................ www.ti.com
TPS51116 employs adaptive on-time control scheme and does not have a dedicated oscillator on board.
However, the device runs with fixed 400-kHz pseudo-constant frequency by feed-forwarding the input and output
voltage into the on-time one-shot timer. The on-time is controlled inverse proportional to the input voltage and
proportional to the output voltage so that the duty ratio is kept as V
OUT
/V
IN
technically with the same cycle time.
Although the TPS51116 does not have a pin connected to VIN, the input voltage is monitored at LL pin during
the ON state. This helps pin count reduction to make the part compact without sacrificing its performance. In
order to secure minimum ON-time during startup, feed-forward from the output voltage is enabled after the output
becomes 750 mV or larger.
TPS51116 can be used for both of DDR (V
VDDQ
= 2.5 V) and DDR2 (V
VDDQ
= 1.8 V) power supply and adjustable
output voltage (0.75 V < V
VDDQ
< 3 V) by connecting VDDQSET pin as shown in Table 1 . Use adjustable output
voltage scheme for DDR3 application.
Table 1. VDDQSET and Output Voltages
VDDQSET VDDQ (V) VTTREF and VTT NOTE
GND 2.5 V
VDDQSNS
/2 DDR
V5IN 1.8 V
VDDQSNS
/2 DDR2
FB Resistors 1.5 V
VDDQSNS
/2 DDR3
R
UP
= R
DOWN
=75 k Ω
FB Resistors Adjustable V
VDDQSNS
/2 0.75 V < V
VDDQ
< 3 V
(1)
TPS51116 integrates high performance low-dropout linear regulator that is capable of sourcing and sinking
current up to 3 A. This VTT linear regulator employs ultimate fast response feedback loop so that small ceramic
capacitors are enough to keep tracking the VTTREF within 40 mV at all conditions including fast load transient.
To achieve tight regulation with minimum effect of wiring resistance, a remote sensing terminal, VTTSNS, should
be connected to the positive node of VTT output capacitor(s) as a separate trace from VTT pin. For stable
operation, total capacitance of the VTT output terminal can be equal to or greater than 20 µ F. It is recommended
to attach two 10- µ F ceramic capacitors in parallel to minimize the effect of ESR and ESL. If ESR of the output
capacitor is greater than 2 m Ω , insert an RC filter between the output and the VTTSNS input to achieve loop
stability. The RC filter time constant should be almost the same or slightly lower than the time constant made by
the output capacitor and its ESR. VTTREF block consists of on-chip 1/2 divider, LPF and buffer. This regulator
also has sink and source capability up to 10 mA. Bypass VTTREF to GND by a 0.033- µ F ceramic capacitor for
stable operation.
In the DDR/DDR2/DDR3 memory applications, it is important to keep VDDQ always higher than VTT/VTTREF
including both start-up and shutdown. TPS51116 provides this management by simply connecting both S3 and
S5 terminals to the sleep-mode signals such as SLP_S3 and SLP_S5 in the notebook PC system. All of VDDQ,
VTTREF and VTT are turned on at S0 state (S3 = S5 = high). In S3 state (S3 = low, S5 = high), VDDQ and
VTTREF voltages are kept on while VTT is turned off and left at high impedance (high-Z) state. The VTT output
is floated and does not sink or source current in this state. In S4/S5 states (S3 = S5 = low), all of the three
outputs are disabled. Outputs are discharged to ground according to the discharge mode selected by MODE pin
(see VDDQ and VTT Discharge Control section). Each state code represents as follow; S0 = full ON, S3 =
suspend to RAM (STR), S4 = suspend to disk (STD), S5 = soft OFF. (See Table 2 )
Table 2. S3 and S5 Control
STATE S3 S5 VDDQ VTTREF VTT
S0 HI HI On On On
S3 LO HI On On Off (Hi-Z)
S4/S5 LO LO Off (Discharge) Off (Discharge) Off (Discharge)
(1) V
VDDQ
≥ 1.2 V when used as VLDOIN.
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