Datasheet

W
PKG
+
T
J(max)
* T
A(max)
q
JA
W
DSNK
+ V
VTT
I
VTT
W
DSRC
+
ǒ
V
VLDOIN
* V
VTT
Ǔ
I
VTT
ESR +
V
OUT
0.015
I
RIPPLE
0.75
[
VOUT
I
OUT(max)
60 [mW]
TI Information — Selective Disclosure
TPS51116
SLUS609I –MAY 2004–REVISED JANUARY 2014 www.ti.com
Equation 25.
(25)
Thermal Design
Primary power dissipation of TPS51116 is generated from VTT regulator. VTT current flow in both source and
sink directions generate power dissipation from the part. In the source phase, potential difference between
VLDOIN and VTT times VTT current becomes the power dissipation, W
DSRC
.
(26)
In this case, if VLDOIN is connected to an alternative power supply lower than VDDQ voltage, power loss can be
decreased.
For the sink phase, VTT voltage is applied across the internal LDO regulator, and the power dissipation, W
DSNK
,
is calculated by Equation 27:
(27)
Because this device does not sink AND source the current at the same time and I
VTT
varies rapidly with time,
actual power dissipation need to be considered for thermal design is an average of above value. Another power
consumption is the current used for internal control circuitry from V5IN supply and VLDOIN supply. V5IN
supports both the internal circuit and external MOSFETs drive current. The former current is in the VLDOIN
supply can be estimated as 1.5 mA or less at normal operational conditions.
These powers need to be effectively dissipated from the package. Maximum power dissipation allowed to the
package is calculated by Equation 28,
(28)
where
• T
J(max)
is 125°C
• T
A(max)
is the maximum ambient temperature in the system
• θ
JA
is the thermal resistance from the silicon junction to the ambient
This thermal resistance strongly depends on the board layout. TPS51116 is assembled in a thermally enhanced
PowerPAD™ package that has exposed die pad underneath the body. For improved thermal performance, this
die pad needs to be attached to ground trace via thermal land on the PCB. This ground trace acts as a heat
sink/spread. The typical thermal resistance, 39.6°C/W, is achieved based on a 6.5 mm × 3.4 mm thermal land
with eight vias without air flow. It can be improved by using larger thermal land and/or increasing vias number.
Further information about PowerPAD™ and its recommended board layout is described in (SLMA002). This
document is available at http:\\www.ti.com.
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