Datasheet

f
0
+
1
2p ESR C
O
v
f
SW
3
R1 +
V
OUT
* 0.75
0.75
R2
f
z1
+
1
2p C
C
R
C
+
f
0
10
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TPS51116
www.ti.com SLUS609I –MAY 2004–REVISED JANUARY 2014
6. Calculate C
C
. The purpose of C
C
is to cut DC component to obtain high DC feedback gain. However, as it
causes phase delay, another zero to cancel this effect at f
0
frequency is need. This zero, ωz1, is determined
by Cc and Rc. Recommended ωz1 is 10 times lower to the f
0
frequency.
(22)
7. When using adjustable mode, determine the value of R1 and R2. .
(23)
D-CAP™ Mode Operation
A buck converter system using D-CAP™ Mode can be simplified as below.
Figure 4. Linearizing the Modulator
The PWM comparator compares the VDDQSNS voltage divided by R1 and R2 with internal reference voltage,
and determines the timing to turn on the high-side MOSFET. The gain and speed of the comparator is high
enough to keep the voltage at the beginning of each on cycle (or the end of off cycle) substantially constant. The
DC output voltage may have line regulation due to ripple amplitude that slightly increases as the input voltage
increase.
For the loop stability, the 0-dB frequency, f
0
, defined below need to be lower than 1/3 of the switching frequency.
(24)
As f
0
is determined solely by the output capacitor’s characteristics, loop stability of D-CAP™ mode is determined
by the capacitor’s chemistry. For example, specialty polymer capacitors (SP-CAP) have C
O
in the order of
several 100 μF and ESR in range of 10 mΩ. These makes f
0
in the order of 100 kHz or less and the loop is then
stable. However, ceramic capacitors have f
0
at more than 700 kHz, which is not suitable for this operational
mode.
Although D-CAP™ mode provides many advantages such as ease-of-use, minimum external components
configuration and extremely short response time, due to not employing an error amplifier in the loop, sufficient
amount of feedback signal needs to be provided by external circuit to reduce jitter level.
The required signal level is approximately 15 mV at comparing point. This gives V
RIPPLE
= (V
OUT
/0.75) x 15 (mV)
at the output node. The output capacitor’s ESR should meet this requirement.
The external components selection is much simple in D-CAP™ mode.
1. Choose inductor. This section is the same as the current mode. Please refer to the instructions in the
Current Mode Operation section.
2. Choose output capacitor(s).Organic semiconductor capacitor(s) or specialty polymer capacitor(s) are
recommended. Determine ESR to meet required ripple voltage above. A quick approximation is shown in
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