Datasheet

4.3
JP1
Non-Tracking Discharge Mode
4.4
JP1
No Discharge Mode
4.5
JP2
R
DS(on)
Current Sensing
4.6
JP2
Resistive Current Sensing
4.7
JP3
D-CAP Control Mode
www.ti.com Configuration
The TPS51116EVM can be configured to operate in non-tracking discharge mode. To operate in
non-tracking discharge mode the TPS51116 must be set in self-driven LDO supply voltage mode because
the TPS51116 sinks up to 3 A from the VDDQ output until V
VDDQ
discharges to 300 mV. If an external
LDO supply is used, selecting non-tracking discharge mode can damage the TPS51116EVM as the LDO
attempts to discharge this external supply and sink upto 3 A.
To program the EVM for non-tracking discharge mode set the JP1 jumper to the upper vertical position.
The TPS51116EVM can be configured to operate in no discharge mode. In no discharge mode, the
TPS51116 simply turns off the supply MOSFETs and leaves the output to be discharged by the load or
self-discharge of the output capacitors.
To program the EVM for no discharge mode set the JP1 jumper to the center horizontal position.
The TPS51116EVM comes preconfigured in a lossless R
DS(on)
current sensing mode. In this mode the
TPS51116EVM uses the forward voltage drop of the low-side MOSFET (Q2) to monitor inductor current. If
a fault is detected, the output voltage droops as output current rises. If a severe over current fault is
detected, it trips the undervoltage comparator. When configured to use R
DS(on)
overcurrent sensing, the
TPS51116 compensates for thermal shift in the R
DS(on)
of the MOSFET.
For R
DS(on)
overcurrent sensing, place a 0- Ω resistor or short at R9 and set the JP2 jumper in the lower
position.
The TPS51116EVM can be configured into a resistive current sense mode. In this mode the
TPS51116EVM senses inductor current by the voltage drop across R8. As with the R
DS(on)
current sensing
mode, the TPS51116 limits the output current allowing V
VDDQ
to droop and trip the undervoltage
comparator output.
To program the EVM for resistive current sensing, ensure the 2-W, 6 m Ω resistor is installed in position
R8, remove any resistor from the R9 position, and set JP2 to the upper position.
The TPS51116EVM is preconfigured to operate in TI’s D-CAP mode. This adaptive constant on-time
semi-hysteretic control scheme combines the benefits of fixed frequency steady-state operation with the
fast transient response of hysteretic control and a minimum off time to prevent inductor saturation or 100%
duty cycle operation. For more information on D-CAP mode, see D-CAP Mode and Transient Load
Response section. Electrolytic output capacitors should always be used when operating in D-CAP mode.
See Appendix A for more information about D-CAP mode.
To program the EVM for D-CAP control mode, set JP3 into the upper position.
SLUU202A – SEPTEMBER 2004 – Revised November 2008 Using the TPS51116EVM 7
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