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User's Guide

SLUU202A – SEPTEMBER 2004 – Revised November 2008

Using the TPS51116EVM

The TPS51116EVM evaluation module (EVM) is a dual-output converter for DDR, DDR2 and DDR3

memory modules. It uses a 10-A synchronous buck converter to provide the core voltage (VDDQ) for DDR

memory modules. The EVM is designed to use a 4.5-V to 28-V supply voltage and a 4.75-V to 5.25-V

controller bias supply. This allows the EVM to start up from a single 5-V supply or operate from a wide

range of supply voltages with low power 5-V bias supply. The TPS51116EVM provides several jumpers

and switches to allow the user to evaluate all of the TPS51116’s configurations including lossless R

DS(on)

or resistive current sensing, current mode or D-CAP™ semi-hysteretic operation, DDR, DDR2 or DDR3

voltage standards and the S3 and S5 sleep states.

Contents

1 Description .................................................................................................................... 2

2 Electrical Performance Specifications ..................................................................................... 3

3 Schematic ..................................................................................................................... 4

4 Configuration ................................................................................................................. 6

5 Test Set-Up ................................................................................................................... 9

6 Power-Up/Power-Down Test Procedures ............................................................................... 11

7 Performance Data and Characteristic Curves .......................................................................... 12

8 EVM Assembly Drawing and Layout .................................................................................... 14

9 List of Materials ............................................................................................................. 17

Appendix A ....................................................................................................................... 18

List of Figures

1 TPS51116 Schematic ....................................................................................................... 5

2 TPS51116EVM Jumper/Switch Locations and Default Positions ..................................................... 6

3 TPS51116EVM Test and Evaluation Setup .............................................................................. 9

4 TPS51116EVM Efficiency ................................................................................................. 12

5 TPS51116EVM 0-A to 8-A Load Transient Response ................................................................ 13

6 TPS51116EVM - 8-A to 0-A Load Transient Response .............................................................. 13

7 Component Outlines ....................................................................................................... 14

8 Top Copper Layer (Top View) ............................................................................................ 15

9 Internal Layer 1 (Top View) ............................................................................................... 15

10 Internal Layer 2 (Top View) ............................................................................................... 16

11 Bottom Copper (Top View) ............................................................................................... 16

List of Tables

1 Electrical Performance Specifications ..................................................................................... 3

2 Jumper Functions ............................................................................................................ 4

3 Adjustable Output Voltage Resistor Values .............................................................................. 8

4 List of Materials ............................................................................................................. 17

D-CAP is a trademark of Texas Instruments.

SLUU202A – SEPTEMBER 2004 – Revised November 2008 Using the TPS51116EVM 1

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Summary of content (20 pages)

PAGE 1
User's Guide SLUU202A – SEPTEMBER 2004 – Revised November 2008 Using the TPS51116EVM The TPS51116EVM evaluation module (EVM) is a dual-output converter for DDR, DDR2 and DDR3 memory modules. It uses a 10-A synchronous buck converter to provide the core voltage (VDDQ) for DDR memory modules. The EVM is designed to use a 4.5-V to 28-V supply voltage and a 4.75-V to 5.25-V controller bias supply.
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Description 1 www.ti.com Description The TPS51116 is designed to be a complete power supply solution for dual data rate (DDR) memory modules covering DDR (2.5 V/1.25 V), and DDR2 (1.8 V/0.9 V) and DDR3 (1.5 V/ 0.75 V) specifications.
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Electrical Performance Specifications www.ti.com 2 Electrical Performance Specifications Table 1. Electrical Performance Specifications PARAMETER VVIN Supply voltage VV5IN Logic supply voltage VVDDQ Switching output voltage TEST CONDITIONS MAX 28 4.75 5.25 2.45 2.50 2.55 DDR2 mode 1.75 1.80 1.85 DDR3 mode 1.45 1.50 1.
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Schematic 3 www.ti.com Schematic The TPS51116EVM schematic is shown in Figure 1. 3.1 Jumpers Standard 100-mil spacing headers JP1 through JP4 provide user configuration settings for the TPS51116EVM. Each jumper bank of three or six pins is provided with a single 100-mil shunt to allow the user to select the desired operation mode. Table 2. Jumper Functions JUMPER 3.2 SELECTION DEFAULT JP1 TPS51116 VDDQ discharge scheme, tracking, non-tracking or no discharge.
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Schematic + + www.ti.com Figure 1.
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Configuration www.ti.com 4 Configuration 4.1 User Selectable Configuration Modes Figure 2 shows the location of the four jumper blocks, two switches and three resistors used to adjust the configuration of TPS51116EVM. Refer to the specific configuration settings sections regarding how to set each jumper, switch or resistor for the specific configuration desired. CAUTION Do not install jumpers in positions other than those shown.
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Configuration www.ti.com 4.3 JP1 Non-Tracking Discharge Mode The TPS51116EVM can be configured to operate in non-tracking discharge mode. To operate in non-tracking discharge mode the TPS51116 must be set in self-driven LDO supply voltage mode because the TPS51116 sinks up to 3 A from the VDDQ output until VVDDQ discharges to 300 mV.
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Configuration 4.8 JP3 www.ti.com Current Mode Control The TPS51116EVM can be configured to operate in a more conventional current mode control. In this mode, the transconductance amplifier’s output is connected to the compensation network. To program the EVM for current mode control, set JP3 into the lower position. 4.9 JP4 DDR Mode The TPS51116EVM can be configured to operate in DDR mode, setting the switching regulator output voltage (VVDDQ) to 2.5 V and the LDO termination voltage (VVTT) to 1.
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Test Set-Up www.ti.com 5 Test Set-Up Figure 3 shows the basic test set up recommended to evaluate the TPS51116EVM. Please note that although all grounds are common, their connections should remain separate as noted in Figure 3. LOAD2 1.25V/0.9V @ 3A - V TT 0 - 5V - + V IN 3 - 28V + + - A1 V1 V5 A5 V2 LOAD3 1.25V/ 0.9V @ <10mA - + LOAD1 2.5V/1.8V @ 10A A2 - + V DD 4.75 - 5.25V V4 V3 + FAN Figure 3. TPS51116EVM Test and Evaluation Setup 5.
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Test Set-Up 5.3 www.ti.com Termination Voltage Source (VTT) VTT source is used to test the sink capability of the VTT LDO. VTT must be able to source 3 A of current at 5 V. A diode should be placed in series with VTT to prevent current from flowing into VTT. VTT should be connected between pins Vtt and Vtt_GND. VTT and LOAD3 should never be powered on at the same time. 5.
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www.ti.com 6 Power-Up/Power-Down Test Procedures Power-Up/Power-Down Test Procedures The following test procedure is recommended primarily for powering up and shutting down the EVM. Whenever the EVM is running the fan should be turned on. Also, never walk away from a powered EVM for extended periods of time. 1. Working at an ESD workstation, make sure that any wrist straps, boot straps or mats are connected referencing the user to earth ground before power is applied to the EVM.
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Performance Data and Characteristic Curves 7 www.ti.com Performance Data and Characteristic Curves The TPS51116EVM is design to provide high efficiency over a very wide range of load currents from maximum load of 10 A down to very light loads less than 100 mA. It is important to achieve high efficiency at very light loads because memory modules consume very little current when waiting for instructions in an idle state. 100 95 D-CAP Mode VOUT = 1.
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Performance Data and Characteristic Curves www.ti.com VOUT = 1.8 V D-CAP Mode VOUT = 1.8 V D-CAP Mode VDDQ (50 mV / div) VDDQ (50 mV / div) IL1 (5 V / div) IL1 (5 V / div) ILOAD (5 A / div) Figure 5. TPS51116EVM 0-A to 8-A Load Transient Response ILOAD (5 A / div) Figure 6. TPS51116EVM - 8-A to 0-A Load Transient Response Figure 5 shows the switching output ripple voltage, the inductor current and the output load current. The advantage of the semi-hysteretic D-CAP mode is clearly visible.
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EVM Assembly Drawing and Layout 8 www.ti.com EVM Assembly Drawing and Layout TPS51116 is built on a 4-layer copper clad FR4 PCB 2.25” x 3.2” and 0.062 thick with all components on a single side. Figure 7 through Figure 11 detail the PCB assembly, silk screen and copper layers for TPS51116EVM. These figures are provided for reference and evaluation purposes only. Figure 7.
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EVM Assembly Drawing and Layout www.ti.com Figure 8. Top Copper Layer (Top View) Figure 9.
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EVM Assembly Drawing and Layout www.ti.com Figure 10. Internal Layer 2 (Top View) Figure 11.
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List of Materials www.ti.com . 9 List of Materials Table 4. List of Materials QTY REFERNCE DESIGNATOR DESCRIPTION SIZE MRF PART NUMBER 2 C3, C4 Capacitor, ceramic, 10 µF, 25 V, X5R, 20% 1210 Vishay C3225X5R1E106M 3 C1, C6, C7 Capacitor, ceramic, 10 µF, 6.3 V, X5R, 10% 805 TDK C2012X5R0J106K 1 C10 Capacitor, ceramic, 0.10 µF, 50 V, X75, 10% 603 Standard Standard 2 C11, C12 Capacitor, POSCAP, 150 µF, 4 V, 45 mΩ, 20% 7343(D) Sanyo 4TPC150M 2 C13, C14 Capacitor, ceramic, 1.
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Appendix A www.ti.com Appendix A A.1 D-CAP Mode and Transient Response TI’s adaptive constant ON-time semi-hysteretic control scheme or D-CAP technology uses VIN and VOUT to determine an ON-time. After this ON-time, the controller waits a minimum off time, then detects a valley in the output voltage, and turns back on after the output voltage has dropped below a threshold voltage.
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FCC Warning This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end-product fit for general customer use. It generates, uses, and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to part 15 of FCC rules, which are designed to provide reasonable protection against radio frequency interference.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.