Datasheet

1 Description
1.1 Applications
1.2 Features
User's Guide
SLUU201–JULY 2004
Using the TPS51100
The TPS51100EVM evaluation module (EVM) includes an LDO for DDRI and DDRII
memory modules with the necessary termination and reference voltages for DDR
Memory modules. The EVM is designed to use a 1.5-V to 3.4-V VDDQ voltage and a
4.75 V to 5.25 V controller core supply to generate the necessary ½ VDDQ termination
voltage with ± 2-A of sink/source current capacity for dual data rate (DDR) memory
modules.
The TPS51100EVM allows the user to evaluate the TPS51100 using an external
reference voltage or the VDDQ LDO supply voltage to test it with DDRI or DDRII
voltage standards and the S3 and S5 sleep states.
The TPS51100 is designed to provide proper termination voltage for DDR memory modules covering both
the DDRI (2.5 V/1.25 V) and DDR2 (1.8 V/0.9 V) specifications with minimal external components. The
high-speed LDO allows designs with fewer and smaller external capacitors, reducing the size and cost of
the dual data rate memory power solution. With the addition of an external regulator to generate the
necessary core and I/O voltage for the memory module, the TPS51100 provides both the termination
voltage and a 10-mA buffered reference voltage necessary to complete the DDRI or DDRII memory power
supply solution.
• Dual data rate (DDR) high-speed RAM termination
• High performance AGP video cards
• Notebook, desktop and sever motherboards
• High performance computer
• High memory content consumer electronics
• High-speed LDO requires only 20-µF (2 × 10-µF) VTT capacitance
• LDO output for DDR termination and buffered reference voltages
•±2-A sink/source termination voltage LDO regulator
• 10-mA termination reference voltage for DDR input reference
• User selectable VDDQ or externally referenced supply voltages
• Switches available for testing S3 and S5 sleep states
Using the TPS511002 SLUU201–JULY 2004