Using the TPS51100 User's Guide Literature Number: SLUU201 JULY 2004
User's Guide SLUU201 – JULY 2004 Using the TPS51100 The TPS51100EVM evaluation module (EVM) includes an LDO for DDRI and DDRII memory modules with the necessary termination and reference voltages for DDR Memory modules. The EVM is designed to use a 1.5-V to 3.4-V VDDQ voltage and a 4.75 V to 5.25 V controller core supply to generate the necessary ½ VDDQ termination voltage with ± 2-A of sink/source current capacity for dual data rate (DDR) memory modules.
www.ti.com Electrical Performance Specifications 2 Electrical Performance Specifications Table 1. Electrical Performance Specifications PARAMETER VV5IN Supply voltage VVDDQ LDO supply voltage VVTT Termination voltage VVTT(tol) Termination voltage tolerance VVTT(RIPPLp-p) Termination voltage ripple (1) TEST CONDITIONS MIN TYP 5.25 1.5 3.
www.ti.com Schematic 3.2 Sleep State Switches Switches SW1 and SW2 select the S5 and S3 sleep states respectively allowing the user to examine the reaction of the TPS51100 controller to these memory sleep states. 3.3 Resistors R1 and R2 Resistors R1 and R2 allow the user to provide a divided reference voltage to the VDDQSNS pin of the TPS51100. If a divided external reference voltage is desired, replace R1 and R2 with the desired resistor ratio.
www.ti.com Test Set-Up 4 Test Set-Up Figure 3 shows the basic test set up recommended to evaluate the TPS51100EVM. Please note that although all grounds are common, their connections should remain separate as noted in. VV5IN 4.75 V to 5.25 V − + V1 − VVDDQ IN 1.3 V to 3.4 V V4 + J5 J1 J3 JP1 + JP2 A3 − VVTT OUT 0 V to 5 V S5 JP4 S3 JP6 + + J7 V2 V3 J8 − LOAD2 1.25 V/ 0.9 V 3A LOAD1 1.25 V/ 0.9 V < 10 mA − FAN Figure 3. TPS51100EVM Recommended Test Set-Up 4.
www.ti.com EVM Assembly Drawing and Layout 4.4 Memory Cell Reference Voltage Load (LOAD1) LOAD1 is an electronic or resistive load sinking less than 10 mA from the VTTREF pin voltage of 1.25 V (DDRI Mode) or 0.9 V (DDRII Mode). LOAD1 should be connected between pins Vtt_Ref and Vtt_Ref_GND 4.5 Termination Voltage Load (LOAD2) LOAD2 is an electronic load set in constant current mode capable of sinking 0 A to 3 A of current at 1.25 V (DDRI Mode) or 0.9 V (DDRII Mode).
www.ti.com EVM Assembly Drawing and Layout Figure 4. Top Side Component Output (Top View) Figure 5. Top Silk Screen (Top View) SLUU201 – JULY 2004 Figure 6. Top Copper Layer (Top View) Figure 7.
www.ti.com List of Materials 6 List of Materials Table 2. List of Materials QT Y 8 REFERNCE DESIGNATOR DESCRIPTION SIZE MRF PART NUMBER Capacitor, ceramic, 10 µF, 6.3 V, X5R, 10% 805 TDK C2012X5R0J106K 3 C1, C5, C6 2 C2, C3 Capacitor, ceramic, 10 µF, 6.3 V, X5R, 10% 1210 TDK C3225X7R1C106M 1 C4 Capacitor, ceramic, 4.7 µF, 6.3-V, X5R, 10% 805 TDK C2012X5R0J475K 0 C7, C8, C9 Capacitor, ceramic, X5R, 6.3V 805 1 C10 Capacitor, ceramic, 0.
FCC Warnings This equipment is intended for use in a laboratory test environment only. It generates, uses, and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to subpart J of part 15 of FCC rules, which are designed to provide reasonable protection against radio frequency interference.
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