Datasheet

TPS51100

SLUS600D –APRIL 2004–REVISED MAY 2012

www.ti.com

LAYOUT CONSIDERATIONS

Consider the following points before the layout of TPS51100 design begins.

• The input bypass capacitor for VLDOIN should be placed to the pin as close as possible with a short and

wide connection.

• The output capacitor for VTT should be placed close to the pin with a short and wide connection in order to

avoid additional ESR and/or ESL of the trace.

• VTTSNS should be connected to the positive node of VTT output capacitor(s) as a separate trace from the

high current power line and is strongly recommended to avoid additional ESR and/or ESL. If it is needed to

sense the voltage of the point of the load, it is recommended to attach the output capacitor(s) at that point.

Also, it is recommended to minimize any additional ESR and/or ESL of the ground trace between the GND

pin and the output capacitor(s).

• Consider adding an LPF at VTTSNS in case the ESR of the VTT output capacitor(s) is larger than 2 mΩ.

• VDDQSNS can be connected separately from VLDOIN. Remember that this sensing potential is the reference

voltage of VTTREF. Avoid any noise generative lines.

• The negative node of the VTT output capacitor(s) and the VTTREF capacitor should be tied together,

avoiding common impedance to the high-current path of the VTT source/sink current.

• The GND (signal GND) pin node represents the reference potential for the VTTREF and VTT outputs.

Connect GND to the negative nodes of the VTT capacitor(s), VTTREF capacitor, and VDDQ capacitor(s) with

care to avoid additional ESR and/or ESL. GND and PGND (Power GND) should be isolated, with a single

point connection between them.

• In order to remove heat from the package effectively, prepare the thermal land and solder to the package

thermal pad. The wide trace of the component-side copper, connected to this thermal land, helps heat

spreading. Numerous vias 0.33 mm in diameter connected from the thermal land to the internal/solder-side

ground plane(s) should be used to help dissipation.

NOTES: 1. The positive terminal of each output capacitor should be directly connected to VTT of the IC; do not use a VIA.

2. The negative terminal of each output capacitor should be directly connected to GND of the IC; do not use a VIA.

3. VIAs

VIA between 1

and 2

layers

VIA between 1

and other layers under 2

4. Rs and Cs with dotted outlines are options.

Figure 1. TPS51100 PCB Layout Guideline

Product Folder Link(s) :TPS51100