Datasheet

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VIN

GND

VDDQSNS

VLDOIN

PGND

VTT

TPS51100DGQ

0.1 µF

5 6VTTREFVTTSNS

2 x 10 µF

VTTREF

5V_IN

Capacitor

Manuf

TDK

Part Number

C2012JB0J106K

C1608JB1H104K

TPS51100

www.ti.com

SLUS600D –APRIL 2004–REVISED MAY 2012

3-A SINK/SOURCE DDR TERMINATION REGULATOR

Check for Samples: TPS51100

FEATURES

The TPS51100 is a 3-A sink/source tracking

• Input Voltage Range: 4.75 V to 5.25 V

termination regulator. It is specifically designed for

• VLDOIN Voltage Range: 1.2 V to 3.6 V

low-cost/low-external component count systems,

where space is a premium.

• 3-A Sink/Source Termination Regulator

Includes Droop Compensation

The TPS51100 maintains fast transient response,

• Requires Only 20-μF Ceramic Output

only requiring 20 μF (2 × 10 μF) of ceramic output

capacitance. The TPS51100 supports remote sensing

Capacitance

functions and all features required to power the DDR

• Supports High-Z in S3 and Soft-Off in S5

and DDR2 VTT bus termination according to the

• 1.2-V Input (VLDOIN) Helps Reduce Total

JEDEC specification. The part also supports DDR3

Power Dissipation

VTT termination with VDDQ at 1.5 V (typ). In addition,

the TPS51100 includes integrated sleep-state

• Integrated Divider Tracks 0.5 VDDQSNS for

controls, placing VTT in high-Z in S3 (suspend to

VTT and VTTREF

RAM) and soft-off for VTT and VTTREF in S5

• Remote Sensing (VTTSNS)

(suspend to disk). The TPS51100 is available in the

• ±20-mV Accuracy for VTT and VTTREF

thermally efficient 10-pin MSOP PowerPAD™

package and is specified from –40°C to 85°C.

• 10-mA Buffered Reference (VTTREF)

• Built-In Soft-Start, UVLO and OCL

ORDERING INFORMATION

• Thermal Shutdown

PLASTIC MSOP PowerPAD™

• Supports JEDEC Specifications

PACKAGE (DGQ)

(1)

–40°C to 85°C TPS51100DGQ

APPLICATIONS

• DDR, DDR2, DDR3 Memory Termination

• SSTL-2, SSTL-18 and HSTL Termination

(1) The DGQ package is also available taped and reeled. Add an

R suffix to the device type (i.e., TPS51100DGQR). See the

application section of the data sheet for the PowerPAD

package drawing and layout information.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2PowerPAD is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (22 pages)

PAGE 1
TPS51100 www.ti.com SLUS600D – APRIL 2004 – REVISED MAY 2012 3-A SINK/SOURCE DDR TERMINATION REGULATOR Check for Samples: TPS51100 FEATURES 1 • • • 2 • • • • • • • • • • Input Voltage Range: 4.75 V to 5.25 V VLDOIN Voltage Range: 1.2 V to 3.6 V 3-A Sink/Source Termination Regulator Includes Droop Compensation Requires Only 20-μF Ceramic Output Capacitance Supports High-Z in S3 and Soft-Off in S5 1.2-V Input (VLDOIN) Helps Reduce Total Power Dissipation Integrated Divider Tracks 0.
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TPS51100 SLUS600D – APRIL 2004 – REVISED MAY 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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TPS51100 www.ti.com SLUS600D – APRIL 2004 – REVISED MAY 2012 ELECTRICAL CHARACTERISTICS TA = –40°C to 85°C, VVIN = 5 V, VLDOIN and VDDQSNS are connected to 2.5 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 0.25 0.5 1 mA 25 50 80 μA 0.3 1 μA 1.2 2 mA 6 10 μA 0.
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TPS51100 SLUS600D – APRIL 2004 – REVISED MAY 2012 www.ti.com ELECTRICAL CHARACTERISTICS (continued) TA = –40°C to 85°C, VVIN = 5 V, VLDOIN and VDDQSNS are connected to 2.5 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT UVLO/LOGIC THRESHOLD Wake up VVINUV UVLO threshold voltage, VIN VIH High-level input voltage S3, S5 VIL Low-level input voltage S3, S5 VIHYST Hysteresis voltage S3, S5 IILEAK Logic input leakage current S2, S5, Hysteresis 3.4 3.7 4 0.15 0.
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TPS51100 www.ti.com SLUS600D – APRIL 2004 – REVISED MAY 2012 SIMPLIFIED BLOCK DIAGRAM VDDQSNS 1 + VLDOIN 6 VTTREF 3 VTT 4 PGND + – – GND 2 HalfDDQ 8 VIN 10 + 3.7 V/3.
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TPS51100 SLUS600D – APRIL 2004 – REVISED MAY 2012 www.ti.com DETAILED DESCRIPTION VTT SINK/SOURCE REGULATOR The TPS51100 is a 3-A sink/source tracking termination regulator designed specially for low-cost, low-externalcomponents systems where space is at premium, such as notebook PC applications. The TPS51100 integrates a high-performance, low-dropout linear regulator that is capable of sourcing and sinking current up to 3 A.
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TPS51100 www.ti.com SLUS600D – APRIL 2004 – REVISED MAY 2012 Output Capacitor For stable operation, total capacitance of the VTT output terminal can be equal to or greater than 20 μF. Attach two 10-μF ceramic capacitors in parallel to minimize the effect of ESR and ESL. If the ESR is greater than 2 mΩ, insert an R-C filter between the output and the VTTSNS input to achieve loop stability.
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TPS51100 SLUS600D – APRIL 2004 – REVISED MAY 2012 www.ti.com LAYOUT CONSIDERATIONS Consider the following points before the layout of TPS51100 design begins. • The input bypass capacitor for VLDOIN should be placed to the pin as close as possible with a short and wide connection. • The output capacitor for VTT should be placed close to the pin with a short and wide connection in order to avoid additional ESR and/or ESL of the trace.
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TPS51100 www.ti.com SLUS600D – APRIL 2004 – REVISED MAY 2012 TYPICAL CHARACTERISTICS VIN SHUTDOWN CURRENT vs TEMPERATURE 1.0 2.0 0.9 1.8 IVINSDN − VINSDN Supply Current − µA IVIN − VIN Supply Current − mA VIN SUPPLY CURRENT vs TEMPERATURE 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0 50 100 1.0 0.8 0.6 0.4 0 50 100 TJ − Junction Temperature − °C G001 Figure 2. Figure 3. VIN SUPPLY CURRENT vs VTT LOAD CURRENT VLDOIN SUPPLY CURRENT vs TEMPERATURE 150 G002 2.0 10 1.9 DDR2 VVTT = 1.
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TPS51100 SLUS600D – APRIL 2004 – REVISED MAY 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) VLDOIN SHUTDOWN CURRENT vs TEMPERATURE DISCHARGE CURRENT vs TEMPERATURE 30 1.8 IDSCHRG − VTT Discharge Current − mA IVLDOINSDN − VLDOINSDN Supply Current − µA 2.0 1.6 1.4 1.2 1.0 0.8 0.6 0.4 20 15 0.2 0.0 −50 0 50 100 10 −50 150 TJ − Junction Temperature − °C 50 100 150 G005 G006 Figure 6. Figure 7.
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TPS51100 www.ti.com SLUS600D – APRIL 2004 – REVISED MAY 2012 TYPICAL CHARACTERISTICS (continued) VTT VOLTAGE LOAD REGULATION vs VTT LOAD CURRENT (DDR3) VTTREF VOLTAGE LOAD REGULATION vs VTTREF LOAD CURRENT (DDR) 0.79 1.252 VVLDOIN = 1.5 V VVTTREF − VTTREF Voltage − V 0.78 VVTT − VTT Voltage − V 0.77 0.76 0.75 0.74 0.73 1.251 1.250 1.249 0.72 0.71 1.248 −3 −2 −1 0 1 2 IVTT − VTT Load Current − A 3 0 2 4 6 8 10 IVTTREF − VTTREF Load Current − mA G009 Figure 10. Figure 11.
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TPS51100 SLUS600D – APRIL 2004 – REVISED MAY 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) VTT VOLTAGE LOAD TRANSIENT RESPONSE STARTUP WAVEFORMS S5 LOW-TO-HIGH VS3 = 0 V IVTT = IVTTREF = 0 A VVLDOIN (50 mV/div) Offset: 1.8 V VS5 (5 V/div) VS3 (5 V/div) VVTT (20 mV/div) Offset 0.9 V VVTTREF (0.5 V/div) VVTTREF (20 mV/div) Offset 0.9 V VVTT (0.5 V/div) IVTT (2 A/div) t − Time − 20 µs/div t − Time − 10 µs/div G013 G014 Figure 14. Figure 15.
PAGE 13
TPS51100 www.ti.com SLUS600D – APRIL 2004 – REVISED MAY 2012 TYPICAL CHARACTERISTICS (continued) SHUTDOWN WAVEFORMS S3 AND S5 HIGH-TO-LOW BODE PLOT DDR SOURCE 180 80 Phase (−1 A) 60 Gain − dB VS3 (5 V/div) VTTREF (0.5 V/div) 135 Phase (−0.1 A) 40 90 20 45 Gain (−0.1 A) 0 0 −20 VVTT (0.5 V/div) −45 C1 = 2 × 10 µF −40 10k 100k IVTT = IVTTREF = 0 A Phase − ° VS5 (5 V/div) Gain (−1 A) −90 10M 1M f − Frequency − Hz t − Time − 1 ms/div G018 G017 Figure 18. Figure 19.
PAGE 14
TPS51100 SLUS600D – APRIL 2004 – REVISED MAY 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) BODE PLOT DDR2 SINK 180 80 60 135 40 90 20 45 0 Phase (0.1 A) Gain (0.1 A) −20 C1 = 2 × 10 µF −40 10k 100k Phase − ° Gain − dB Phase (1 A) 0 −45 Gain (1 A) 1M −90 10M f − Frequency − Hz G021 Figure 22.
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TPS51100 www.ti.com SLUS600D – APRIL 2004 – REVISED MAY 2012 Changes from Revision C (JUNE 2008) to Revision D • Page Added updated Thermal data ...............................................................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
PAGE 17
PACKAGE MATERIALS INFORMATION www.ti.com 8-May-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPS51100DGQR Package Package Pins Type Drawing MSOPPower PAD DGQ 10 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 5.3 B0 (mm) K0 (mm) P1 (mm) 3.4 1.4 8.0 W Pin1 (mm) Quadrant 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 8-May-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS51100DGQR MSOP-PowerPAD DGQ 10 2500 364.0 364.0 27.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.