Datasheet

( )
J(max) A(max)
PKG
JA
T T
W
-
=
q
DSNK VTT VTT
W V I= ´
( )
DSRC VLDOIN VTT VTT
W V V I= - ´
OUT VTT
SS
VTTOCL
C V
t
I
æ ö
´
=
ç ÷
è ø
TPS51100
www.ti.com SLUS600D –APRIL 2004–REVISED MAY 2012
Output Capacitor
For stable operation, total capacitance of the VTT output terminal can be equal to or greater than 20 μF. Attach
two 10-μF ceramic capacitors in parallel to minimize the effect of ESR and ESL. If the ESR is greater than 2 mΩ,
insert an R-C filter between the output and the VTTSNS input to achieve loop stability. The R-C filter time
constant should be almost the same or slightly lower than the time constant of the output capacitor and its ESR.
Soft-start duration, t
SS
, is also a function of this output capacitance. Where I
TTOCL
= 2.2 A (typ), t
SS
can be
calculated as,
(1)
Input Capacitor
Depending on the trace impedance between the VLDOIN bulk power supply to the part, transient increase of
source current is supplied mostly by the charge from the VLDOIN input capacitor. Use a 10-μF (or more) ceramic
capacitor to supply this transient charge. Provide more input capacitance as more output capacitance is used at
VTT. In general, use 1/2 C
OUT
for the input.
VIN Capacitor
Add a ceramic capacitor with a value between 1 μF and 4.7 μF placed close to the VIN pin, to stabilize 5 V from
any parasitic impedance from the supply.
Thermal Design
As the TPS51100 is a linear regulator, the VTT current flow in both source and sink directions generates power
dissipation from the device. In the source phase, the potential difference between V
VLDOIN
and V
VTT
times VTT
current becomes the power dissipation, W
DSRC
.
(2)
In this case, if VLDOIN is connected to an alternative power supply lower than V
DDQ
voltage, power loss can be
decreased.
For the sink phase, VTT voltage is applied across the internal LDO regulator, and the power dissipation, and
W
DSNK
, is calculated by:
(3)
Because the device does not sink and source the current at the same time and I
VTT
varies rapidly with time, the
actual power dissipation that must be considered for thermal design is an average over the thermal relaxation
duration of the system. Another power consumption is the current used for internal control circuitry from the VIN
supply and VLDOIN supply. This can be estimated as 20 mW or less at normal operational conditions. This
power must be effectively dissipated from the package. Maximum power dissipation allowed to the package is
calculated by,
(4)
where
T
J(max)
is 125°C
T
A(max)
is the maximum ambient temperature in the system
θ
JA
is the thermal resistance from the silicon junction to the ambient
This thermal resistance strongly depends on the board layout. TPS51100 is assembled in a thermally enhanced
PowerPAD package that has an exposed die pad underneath the body. For improved thermal performance, this
die pad must be attached to the ground trace via thermal land on the PCB. This ground trace acts as a heat
sink/spread. The typical thermal resistance, 57.7°C/W, is achieved based on a 3 mm × 2 mm thermal land with
two vias without air flow. It can be improved by using larger thermal land and/or increasing the number of vias.
For example, assuming a 3 mm × 3 mm thermal land with four vias without air flow, it is 45.4°C/W. Further
information about the PowerPAD package and its recommended board layout is described in the PowerPAD
Thermally Enhanced Package application report (SLMA002). This document is available at www.ti.com.
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