Datasheet

TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240A – SEPTEMBER 1999 – REVISED MAY 2001
28
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
layout guidelines (continued)
When configuring the high-side driver as a floating driver, the connection from LL to the power FETs should
be as short and as wide as possible.
When configuring the high-side driver as a floating driver, the bootstrap capacitor (connected from LH to
LL) should be placed close to the TPS5103.
When configuring the high-side driver as a ground-referenced driver, LL should be connected to DRVGND.
The bulk-storage capacitors across V
I
should be placed close to the power FETS. High-frequency bypass
capacitors should be placed in parallel with the bulk capacitors and connected close to the drain of the
high-side FET and to the source of the low-side FET.
High-frequency bypass capacitors should be placed across the bulk-storage capacitors on V
O
.
LH and LL should be connected very close to the drain and source, respectively, of the high-side FET. LH
and LL should be routed very close to each other to minimize differential-mode noise coupling to these
traces. Ceramic-decoupling capacitors should be placed close to where V
CC
connects to V
I
, to reduce
high-frequency noise coupling on V
CC
.
The output-voltage sensing trace should be isolated by either ground trace or V
CC
trace.
test results
The tests are conducted at T
A
= 25°C, the point voltage is 5 V.