Datasheet

TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240A – SEPTEMBER 1999 – REVISED MAY 2001
27
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
synchronization (continued)
TPS5103
C
T
R
T
740 mV
740 mV
Figure 46. Triangle-Wave Synchronization
Square-wave synchronization
It can be seen that R
T
and C
T
are removed from the circuit. Therefore, two components are saved. This method
is good for the synchronization between two controllers. If the controller needs to be synchronized with a digital
circuit such as a DSP, usually the square-type clock signal is used. The configuration shown in Figure 47 is for
this type of application.
TPS5103
C
T
R
T
Figure 47. Square-Wave Synchronization
An external resistor is added into the circuit, but R
T
is still removed. C
T
is kept to be a part of the RC circuit
generating the triangle waveform for the controller. Assuming the peak value of the square is known, the resistor
and the capacitor can be adjusted to achieve the correct peak-to-peak value and the offset value.
layout guidelines
Good power supply results will only occur when care is given to proper design and layout. Layout will affect noise
pickup and generation, and can cause a good design to perform with less than expected results. With a range
of currents from milliamps to tens or even hundreds of amps, good power-supply layout is much more difficult
than most general PCB designs. The general design should proceed from the switching node to the output, then
back to the driver section and, finally, place the low-level components. Below are several specific points to
consider before layout of a TPS5103 design begins.
All sensitive analog components should be referenced to ANAGND. These include components connected
to VREF5, Vref, INV, LH, and COMP .
Analog ground and drive ground should be isolated as much as possible. Ideally, analog ground will connect
to the ground side of the bulk storage capacitors on V
O
, and drive ground will connect to the main ground
plane close to the source of the low-side FET.
Connections from the drivers to the gate of the power FETs should be as short and wide as possible to
reduce stray inductance. This becomes more critical if external gate resistors are not being used.
The bypass capacitor for V
CC
should be placed close to the TPS5103.