Datasheet

TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240A – SEPTEMBER 1999 – REVISED MAY 2001
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
loop-gain compensation (continued)
_
+
R4
C3
C2
R2R1
C1
R3
V
ref
To PWM
Figure 43. Typical Compensation Circuit
This circuit is composed of one integrator, two poles, and two zeros.
Assuming R1 << R2 and C2 << C3, the equation i
s:
Comp
(
1 sC3R4
) (
1 sC2R2
)
sC3R2
(
1 sC2R4
)(
1 sC1R1
)
Therefore,
Pole 1
1
2 C1R1
Pole 2
1
2 C2R4
Zero 2
1
2 C3R4
Zero 1
1
2 C2R2
Integrator
1
2 ƒC3R2
A simplified version used in the EVM design is shown in Figure 44.
_
+
R4
C3
C2
R2
V
O
R3
V
ref
NOTE: R2 > 10 kΩ
Figure 44. Simplified Compensation Circuit
Assuming C2 << C3, the equation is:
Comp
(
1 sC3R4
)
sC3R2
(
1 sC2R4
)