Datasheet



SLUS564C − JULY 2003 − REVISED OCTOBER 2008
7
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Figure 1
V
SSTRT
− Soft-Start Voltage − V
t − Time
f
SW
− Switching Frequency − kHz
R
SSTRT1
= R
SSTRT2
= OPEN = 450 kHz
270 360
470
360
470 270
1.2
3.6
5.0
1.5
1.2
3.6
5.0
1.5
0
0
t1t0 t3t2 t4 t5
ENBL1
ENBL2
A
B
SSTRT1
SSTRT2
C
A
B
C
Figure 2
t − Time
f
SW
− Switching Frequency − kHz
270
360
270
360
270
1.2
3.6
5.0
1.5
1.2
3.6
5.0
1.5
0
0
t1t0 t3t2 t4 t5
ENBL1
ENBL2
SSTRT1
SSTRT2
R
SSTRT1
= 1 MΩ, R
SSTRT2
= OPEN = 360 kHz
V
SSTRT
− Soft-Start Voltage − V
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME NO.
I/O
DESCRIPTION
COMP1 2 O
Error amplifier output. Connect feedback network to this pin and INVx for compensation of control loop.
COMP2 14 O
Error amplifier output. Connect feedback network to this pin and INVx for compensation of control loop.
DDR 6 I
DDR selection pin. If this pin is grounded, the device runs in DDR Mode. The error amplifier reference for VO2
is (VO1_VDDQ)/2, the REF_X output voltage becomes (VO1_VDDQ)/2 and skip mode is disabled for VO2,
Also, VREG5 is turned off when both ENBLx are at low in this mode. If this pin is at 2.2-V or higher, the device
runs in ordinary dual SMPS mode (dual mode), then the error amplifier reference for VO2 is connected to inter-
nal 0.85-V reference, the REF_X output voltage becomes 10 V, VREG5 is kept on regardless of ENBLx status.
CAUTION: Do not toggle DDR
while ENBL1 or ENBL2 are high. (See Table 2)
ENBL1 9 I
TTL Enable Input. If ENBLx is greater than 2.2 V, then the VREG5 is enabled (DDR mode) and the SMPS o
f
that channel attempts to turn on. If both ENBL1 and ENBL2 are low then the 10-V (or (VO1_VDDQ)/2 output)
ENBL2 10 I
that channel attempts to turn on. If both ENBL1 and ENBL2 are low then the 10-V (or (VO1_VDDQ)/2 output)
voltage as well as the oscillator are turned off. (See Table 2)
GND 7 O Signal ground pin.
INV1 1 I
Error amplifier inverting input. Also input for skip comparator, and OVP/UVP comparators.
INV2 15 I
Error amplifier inverting input. Also input for skip comparator, and OVP/UVP comparators.
LL1 28 I/O
Switch-node connection for high-side driver and overcurrent protection circuitry.
LL2 18 I/O
Switch-node connection for high-side driver and overcurrent protection circuitry.
OUT1_D 27 O
Synchronous N-channel MOSFET driver output.
OUT2_D 19 O
Synchronous N-channel MOSFET driver output.
OUT1_U 29 O
High-side N-channel MOSFET driver output.
OUT2_U 17 O
High-side N-channel MOSFET driver output.
OUTGND1 26 O
Ground return for OUTx_D.
OUTGND2 20 O
Ground return for OUTx_D.