Datasheet

TPS43330-Q1
TPS43332-Q1
SLVSA82E –MARCH 2011–REVISED APRIL 2013 www.ti.com
THERMAL INFORMATION
TPS4333x-Q1
THERMAL METRIC
(1)
DAP UNIT
38 PINS
θ
JA
Junction-to-ambient thermal resistance
(2)
27.3 °C/W
θ
JCtop
Junction-to-case (top) thermal resistance
(3)
19.6 °C/W
θ
JB
Junction-to-board thermal resistance
(4)
15.9 °C/W
ψ
JT
Junction-to-top characterization parameter
(5)
0.24 °C/W
ψ
JB
Junction-to-board characterization parameter
(6)
6.6 °C/W
θ
JCbot
Junction-to-case (bottom) thermal resistance
(7)
1.2 °C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψ
JT
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψ
JB
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
RECOMMENDED OPERATING CONDITIONS
MIN MAX UNIT
Input voltage: VIN, VBAT 4 40
Enable inputs: ENA, ENB 0 40
Boot inputs: CBA, CBB 4 48
Buck function:
BuckA and BuckB Phase inputs: PHA, PHB –0.6 40 V
voltage
Current-sense voltage: SA1, SA2, SB1, SB2 0 11
Power-good output: PGA, PGB 0 11
SYNC, EXTSUP 0 9
Enable input: ENC 0 9
Boost function Voltage sense: DS 40 V
DIV 0 V
REG
Operating temperature: T
A
–40 125 °C
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