Datasheet

DELAY
DLYAB
t 1 msec
=
C 1 nF
SW
S
L f
200
R
´
=
TPS43330-Q1
TPS43332-Q1
SLVSA82E –MARCH 2011–REVISED APRIL 2013 www.ti.com
Slope Compensation
Optimal slope compensation, which is adaptive to changes in input voltage and duty cycle, allows stable
operation under all conditions. For optimal performance of this circuit, choose the inductor and sense resistor
according to the following:
where
L is the buck-regulator inductor in henries.
R
S
is the sense resistor in ohms.
f
sw
is the buck-regulator switching frequency in hertz.
Power-Good Outputs and Filter Delays
Each buck controller has an independent power-good comparator monitoring the feedback voltage at the FBx
pins and indicating whether the output voltage has fallen below a specified power-good threshold. This threshold
has a typical value of 93% of the regulated output voltage. The power-good indicator is available as an open-
drain output at the PGx pins. An internal 50-kΩ pullup resistor to Sx2 is available, or use of an external resistor is
possible. Shutdown of a buck controller causes an internal pulldown of the power-good indicator. Connecting the
pullup resistor to a rail other than the output of that particular buck channel causes a constant current flow
through the resistor when the buck controller is powered down.
In order to avoid triggering the power-good indicators due to noise or fast transients on the output voltage, the
device uses an internal delay circuit for de-glitching. Similarly, when the output voltage returns to its set value
after a long negative transient, assertion of the power-good indicator (release of the open-drain pin) occurs after
the same delay. Use of this delay can pause the reset of circuits powered from the buck regulator rail. Program
the duration of the delay by using a suitable capacitor at the DLYAB pin according to the equation:
When the DLYAB pin is open, the delay setting is for a default value of 20 µs typical. The power-good delay
timing is common to both the buck rails, but the power-good comparators and indicators function independently.
Light-Load PFM Mode
An external clock or a high level on the SYNC pin results in forced continuous-mode operation of the bucks. An
open or low on the SYNC pin allows the buck controllers to operate in discontinuous mode at light loads by
turning off the low-side MOSFET on detection of a zero-crossing in the inductor current.
In discontinuous mode, as the load decreases, the duration when both the high-side and low-side MOSFETs turn
off increases (deep discontinuous mode). In case the duration exceeds 60% of the clock period and V
BAT
> 8 V,
the buck controller switches to a low-power operation mode. The design ensures that this typically occurs at 1%
of the set full-load current if the choice of the inductor and sense resistor is as recommended in the slope-
compensation section.
In low-power PFM mode, the buck monitors the FBx voltage and compares it with the 0.8-V internal reference.
Whenever the FBx value falls below the reference, the high-side MOSFET turns on for a pulse duration inversely
proportional to the difference VIN – Sx2. At the end of this on-time, the high-side MOSFET turns off and the
current in the inductor decays until it becomes zero. The low-side MOSFET does not turn on. The next pulse
occurs the next time FBx falls below the reference value. This results in a constant volt-second t
on
hysteretic
operation with a total device quiescent current consumption of 30 µA when a single buck channel is active and
35 µA when both channels are active.
As the load increases, the pulses become more and more frequent and move closer to each other until the
current in the inductor becomes continuous. At this point, the buck controller returns to normal fixed-frequency
current-mode control. Another criterion to exit the low-power mode is when VIN falls low enough to require higher
than 80% duty cycle of the high-side MOSFET.
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