Datasheet

TPS43330-Q1

TPS43332-Q1

www.ti.com

SLVSA82E –MARCH 2011–REVISED APRIL 2013

PIN FUNCTIONS (continued)

NAME NO. I/O DESCRIPTION

Soft-start or tracking input for buck controller BuckB. The buck controller regulates the FBB voltage to the lower of

0.8 V or the SSB pin voltage. An internal pullup current source of 1 µA is present at the pin, and an appropriate

SSB 25 O

capacitor connected here sets the soft-start ramp interval. Alternatively, a resistor divider connected to another

supply can provide a tracking input to this pin.

If an external clock is present on this pin, the device detects it and the internal PLL locks onto the external clock,

this overriding the internal oscillator frequency. The device can synchronize to frequencies from 150 kHz to 600

kHz. A high logic level on this pin ensures forced continuous-mode operation of the buck controllers and inhibits

SYNC 20 I

transition to low-power mode. An open or low allows discontinuous-mode operation and entry into low-power

mode at light loads. On the TPS43332-Q1, a high level enables frequency-hopping spread spectrum, whereas an

open or a low level disables it.

Battery input sense for the boost controller. If, with the boost controller enabled, the voltage at VBAT falls below

VBAT 1 I the boost threshold, the device activates the boost controller and regulates the voltage at VIN to the programmed

boost output voltage.

Main Input pin. This is the buck-controller input pin as well as the output of the boost regulator. Additionally, VIN

VIN 38 I

powers the internal control circuits of the device.

The device requires an external capacitor on this pin to provide a regulated supply for the gate drivers of the buck

VREG 35 O and boost controllers. TI recommends capacitance on the order of 4.7 µF. The regulator obtains its power from

either VIN or EXTSUP. This pin has current-limit protection; do not use it to drive any other loads.

Product Folder Links: TPS43330-Q1 TPS43332-Q1