Datasheet

Time = 400 ns/div

10.0 V/div

C2: HDRV

C1: SW

5.00 V/div

C3: LDRV

Time = 5.00 ms/div

5.00 V/div

C2: VCC

C3: V

OUT

5.00 V/div

C1: V

5.00 V/div

C4: PGOOD

Time = 200 ms/div

5.00 V/div

C2: VCC

C3: V

OUT

5.00 V/div

C1: EN

5.00 V/div

C4: PGOOD

Test Setup and Results

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2.8 Shutdown

The shutdown waveforms are shown in Figure 14 and Figure 15. In Figure 14 the input voltage is

removed, and when the input falls below the undervoltage lockout threshold set by the EN resistor divider,

the TPS43061 shuts down, PGOOD is pulled low and the output falls to ground. The output has a 2-A

resistive load.

In Figure 15 the input voltage is held at 9 V with no load and EN is shorted to ground. When EN is

grounded, the TPS43061 is disabled, PGOOD is pulled low and the output voltage discharges to VIN.

Figure 14. Shutdown Relative to V

Figure 15. Shutdown Relative to EN

2.9 Gate-Drive Signals

In Figure 16 the gate-drive signals for the high-side and low-side FETs can be seen with the switching

node are shown. The input voltage is 9 V and the output has a 2-A load.

Figure 16. Gate-Drive Signals

Using the TPS43061 Boost Evaluation Module (EVM) SLVU799A–November 2012–Revised March 2013

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