Datasheet
( )
( )
_
_ _
_
_ _ _
221 1.14
4.3 1.14 221 1.8 3.2
59
EN hys
UVLO H EN DIS
UVLO L
STOP EN DIS UVLO H EN pup
R V
k V
R
V V k A A
V V R I I
k
´
W ´
= =
- + W ´ m + m
- + ´ +
= W
_
_
_
_
_ _
_
1.14
5.34 4.3
1.21
221.26
1.14
1.8 1 3.2
1
1.21
EN DIS
START STOP
EN ON
UVLO H
EN DIS
EN pus EN hys
EN ON
V
V
V V
V V
V
V
R k
V
V
A A
I I
V
V
æ ö
æ ö
´ -
ç ÷
´ -
ç ÷ ç ÷
è ø è ø
= = = W
æ ö æ ö
m ´ - + m
ç ÷
´ - +
ç ÷
ç ÷
è ø
è ø
20 5
0.082
1.22
SS SS
SS
REF
t I
ms A
C F
V V
´
´ m
= = = m
15 1.22
11.0 124.2
1.22
OUT FB
HS LS
FB
V V
V V
R R k k
V V
-
-
= ´ = W ´ = W
TPS43060
TPS43061
SLVSBP4C –DECEMBER 2012–REVISED SEPTEMBER 2013
www.ti.com
OUTPUT VOLTAGE AND FEEDBACK RESISTORS SELECTION
The voltage divider of R8 and R9 sets the output voltage. To balance power dissipation and noise sensitivity, R9
should be selected between 10 kΩ and 100 kΩ. For the example design, 11 kΩ was selected for R9. Using
Equation 33, R8 is calculated as 124.2 kΩ. The nearest standard 1% resistor 124 kΩ is used.
(33)
Where R
LS
= R9 and R
HS
= R8.
SETTING THE SOFT-START TIME
The soft-start capacitor determines the amount of time allowed for the output voltage to reach its nominal
programmed value during power up. This is especially useful if a load requires a controlled voltage slew rate. A
controlled start-up time is necessary with large output capacitance to limit the current into the capacitor during
start-up. Large currents to charging the capacitor during start-up could trigger the devices current limit. Excessive
current draw from the input power supply may also cause the input voltage rail to sag. The soft-start capacitor
can be sized to limit in-rush current or output voltage overshoot during startup. Use Equation 34 to calculate the
required capacitor for a desired soft-start time. In this example application for a desired soft-start time of 20 ms, a
0.082 µF capacitance is calculated, and the nearest standard value of 0.1 µF capacitor is chosen.
(34)
UNDERVOLTAGE LOCKOUT SET POINT
The undervoltage lockout (UVLO) can be adjusted using an external voltage divider connected to the EN pin of
the TPS43060 and TPS43061. The UVLO has two thresholds, one for power up when the input voltage is rising
and one for power down or brown outs when the input voltage is falling. The necessary voltage divider resistors
are calculated with Equation 35 and Equation 36. If the application does not require an adjustable UVLO, the EN
pin can be left floating or tied to the VIN pin.
For the example design, the supply should start switching once the input voltage increases to 5.34 V (V
START
).
After start-up, it should continue to operate until the input voltage falls to 4.3 V (V
STOP
). To produce the desired
start and stop voltages, resistor divider values R3 = 221 kΩ between VIN and EN and a R4 = 59 kΩ between EN
and GND are used.
(35)
(36)
POWER GOOD RESISTOR SELECTION
The PGOOD pin is an open drain output requiring a pull-up resistor connected to a voltage supply of no more
than 8 V. A value between 10 kΩ and 100 kΩ is recommended. If the Power Good indicator feature is not
needed, this pin can be grounded or left floating.
THE CONTROL LOOP COMPENSATION
There are several methods to design compensation for DC-DC regulators. The method presented here is easy to
calculate and ignores the effects of the slope compensation internal to the device. Since the slope compensation
is ignored, the actual crossover frequency will be lower than the crossover frequency used in the calculations.
This method assumes the crossover frequency is between the modulator pole and ESR zero of the output
capacitor. In this simplified model, the DC gain (Adc), modulator pole (ƒ
Pmod
), and the ESR zero (ƒ
Zmod
) are
calculated with Equation 37 to Equation 39. Use the de-rated value of C
OUT
, which is 22 µF in this example. In a
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