Datasheet

TPS40400
SLUS930B APRIL 2011 REVISED OCTOBER 2011
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
Unless otherwise stated, these specifications apply for 40°C T
J
125°C, V
DD
= 12 Vdc, FREQUENCY_SWITCH = 600 kHz
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OUTPUT VOLTAGE MARGINING
VFB slope during margin voltage transition
(8)
Factory default settings 250 214 188 V/s
MRG
SLP
Accuracy 3 V < V
VDD
< 20 V, 600 μs < t
SS
< 9 ms 15% 15%
V
FBMH
FB pin voltage after margin high command Factory default settings 650 660 670 mV
V
FBML
FB pin voltage after margin low command Factory default settings 532 540 548 mV
V
FBM(max)
Maximum FB pin voltage with Margin 40°C < T
J
< 125°C 742 750 758 mV
V
FBM(min)
Minimum FB pin voltage with Margin 40°C < T
J
< 125°C 445 450 455 mV
V
FB(inc)
Resolution of FB steps with margin 2.34 mV
OVERVOLTAGE AND UNDERVOLTAGE DETECTION
FB pin overvoltage threshold (OV flag) Factory default settings 638 672 705
V
OV
mV
Accuracy 3 V < V
VDD
< 20 V, 648 mV < V
OV
< 690 mV 5% 5%
FB pin undervoltage threshold (UV flag) Factory default settings 502 528 554
V
UV
mV
3 V < V
VDD
< 20 V,
Accuracy 5% 5%
510 mV < V
OV
< 552 mV
PMBus INTERFACE
V
IH
High-level input voltage, CLK, DATA, CNTL 2.1 V
V
IL
Low-level input voltage, CLK, DATA, CNTL 0.8 V
High-level input current, CLK, DATA, CNTL 10 10
I
IH
μA
CNTL 12 10
Low-level input current, CLK, DATA, CNTL 10 10
I
IL
μA
CNTL 12 10
V
OL
Low-level output voltage, DATA, SMBALRT 3.0 V V
VDD
20 V, I
OUT
= 2 mA 0.4 V
High-level open drain leakage current, DATA,
I
OH
V
OUT
= 3.6 V 0 10 μA
SMBALRT
C
O
(8)
Pin capacitance, CLK, DATA 0.7 pF
f
PMB
PMBus operating frequency range Slave mode 10 400 kHz
t
BUF
Bus free time between START and STOP
(8)
4.7 μs
t
HD:STA
Hold time after repeated START
(8)
4.0 μs
t
SU:STA
Repeated START setup time
(8)
4.7 μs
t
SU:STO
STOP setup time
(8)
4.0 μs
Receive mode 0
t
HD:DAT
Data hold time
(8)
ns
Transmit mode 300
t
SU:DAT
Data setup time
(8)
250 ns
t
TIMEOUT
Error signal/detect
(8)
25 35 μs
t
LOW:MEXT
Cumulative clock low master extend time
(8)
50 μs
t
LOW:SEXT
Cumulative clock low slave extend time
(8)
25 μs
t
LOW
Clock low time
(8)
4.7 μs
t
HIGH
Clock high time
(8)
4.0 μs
t
FALL
CLK/DATA fall time
(8)
300 ns
t
RISE
CLK/DATA rise time
(8)
1000 ns
PMBus ADDRESSING
I
ADD
ADDX pin current 8.23 9.75 11.21 μA
V
ADD(L)
Address pin illegal low voltage threshold 0.055 V
(8) Ensured by design. Not production tested.
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