Datasheet

( )
GHS
BOOT
BOOT ripple
Q
8nC
C C9 40nF
V 0.2 V
= ³ ´ =
( )
2
SW
Energy E 1
f 2 events C V 300kHz
sec onds cycle 2
= ´ = ´ ´ ´ ´
2
60mW 60mW
C 1.02nF
196 300kHz
V 300kHz
= = =
´
´
Shortest Pulse Width
28.6n 28.6n
10
R 5.72
5 C 5 C 5 1n
= = = = W
´ ´ ´
REF
BIAS
OUT REF
V R1
R
V V
´
=
-
TPS40400
SLUS930B –APRIL 2011– REVISED OCTOBER 2011 www.ti.com
Bootstrap Capacitor, C9
Selection of the bootstrap capacitor is based on the total gate charge of the high-side FET and the allowable
ripple on the BOOT pin. A ripple of 0.2 V is chosen as maximum for this design. This yields a value described in
Equation 49.
(49)
Choose a standard value of 100 nF. Additionally, a series resistor R9 is added in order to reducing the turn-on
speed of the high-side FET, Q1.
Snubber R12 and C16
For this design, the snubber function is designed based on an allowable snubber power dissipation. A target
value of between 0.25% and 0.5% of the rated output power (P
OUT
) is used as the starting point for the
calculation of the snubber values. Once the snubber values are determined and real hardware is obtained, the
snubber values can be adjusted to achieve better results.
(50)
(51)
(52)
Loop Compensaton Components
Using the Texas Instruments SwitcherPro™ design tool and the resulting plant (system) bode plot, a crossover
frequency of 20 kHz is selected with 45° of phase margin. The resulting compensation components are listed in
Table 6.
Table 6. Deisgn Example 1 Component Summary
COMPONENT LOCATION VALUE
R6 4.99 kΩ
R8 2.74 kΩ
C6 680 pF
C7 2.2 nF
C8 820 pF
Output Voltage Set Point, R
BIAS
The output voltage can be set by choosing and calculating R1 and R
BIAS
. The V
OUT
set point is shown in
Equation 53.
(53)
In this design R1 was chosen to be 10 kΩ. R
BIAS
is calculated to be 10 kΩ.
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