Datasheet

L1
DCR
t =
L1 1 750nH
R16 6.25k
DCR C 1.2m 100nF
= ´ = = W
W ´
TPS40400
www.ti.com SLUS930B –APRIL 2011– REVISED OCTOBER 2011
Device Addressing, R
ADDR0
and R
ADDR1
The PMBus address for the device must be read from the ADDR0 and ADDR1 pins. Each pin has an internal
fixed current source and the resulting developed voltage is read and converted to the desired device address.
The external resistors R
ADDR0
and R
ADDR1
from the address pins to ground set eight possible states for a total of
64 possible addresses. The address states are determined by voltages on the address pins per Table 4.
Table 4. Address
Configuration
DIGIT RESISTANCE (kΩ)
0 10
1 15.4
2 23.7
3 36.5
4 54.9
5 84.5
6 130
7 200
For this design, the address of 34 octal, or 28 decimal is selected arbitrarily. In order to achieve this address, the
ADDR0 resistor R5 would be 54.9 kΩ and the ADDR1 resistor R4 would be 36.5 kΩ.
Current Sense Flter, R16 and C17
Current sensing for the TPS40400 is typically done by sensing the voltage drop across the output inductor’s (L1)
DC resistance. In order to do this, the large AC switching voltage forced across L1 must be filtered out so that
the measured voltage is only the DC drop. This is done by placing an R-C filter directly across the output choke
(high-frequency filter) L1. The R-C combination is chosen such that it provides enough filtering for the application
and the time constant is chosen to match that of the output inductor and its ESR, which is shown in Equation 47.
(47)
Usually a capacitor value is chosen between 10 nF and 1 µF for this location. A value of 100 nF is arbitrarily
chosen, which yields Equation 48.
(48)
Choose a standard value of 6.19 kΩ.
The capacitor C17 should be placed as close to the ISNS+ and ISNS– pins as possible to provide good bypass
filtering. R16 should be placed close to the inductor to prevent traces with the switch node voltage from being
propagated across the PCB and getting close to sensitive pins of the TPS40400.
Voltage Decoupling Capacitors, C
BP3
, C
BP6
, and C
VDD
Three pins on the TPS40400 have DC bias voltages. It is necessary to add small decoupling capacitors to these
pins. Table 5 shows the recommended minimum values.
Table 5. Voltage Decoupling Capacitor Values
RECOMMENDED
DEVICE LOCATION FUNCTION SELECTED VALUE
MINIMUM VALUE
V
CC
for internal controls of the
C
BP3
, (C18) 0.1-µF low ESR 1-µF ceramic
device
C
BP6
, (C15) 1-µF low ESR V
CC
for gate drivers 1-µF ceramic
2 x 100 nF, with additional series 10-Ω filter
C
VDD
, (C1) and (C2) 0.1-µF low ESR V
CC
for input power to the device resistor R3 to filter out switching noise from the
power FETs
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