Datasheet
TPS40400
www.ti.com
SLUS930B –APRIL 2011– REVISED OCTOBER 2011
ELECTRICAL CHARACTERISTICS (continued)
Unless otherwise stated, these specifications apply for –40°C ≤ T
J
≤ 125°C, V
DD
= 12 Vdc, FREQUENCY_SWITCH = 600 kHz
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OUTPUT DRIVERS
(V
BOOT
– V
SW
) = 6.4 V, I
HDRV
= –100 ,
R
HDHI
High-side driver pull up resistance 1.25 2.5
T
J
= 25°C
(V
BOOT
– V
SW
) = 6.4 V, I
HDRV
= 100 mA,
R
HDLO
High-side driver pull down resistance 1.3 2.6
Ω
T
J
= 25°C
R
LDHI
Low-side driver pull up resistance T
J
= 25°C 1.25 2.5
R
LDLO
Low-side driver pull down resistance T
J
= 25°C 0.8 1.5
t
HRISE
High-side driver rise time
(6)
6 12.1
t
HFALL
High-side driver fall time
(6)
6.3 12.6
C
LOAD
= 2.2 nF ns
t
LRISE
Low-side driver rise time
(6)
6 12.1
t
LFALL
Low-side driver fall time
(6)
4 8
MFR_SPECIFIC_00 bit 0 = 0,
t
DT
Anti-cross conduction time 20 50 ns
(short dead time.)
I
SW
SW pin leakage current (out of pin) V
SW
= 0 V 1 μA
BOOTSTRAP
V
BOOT
Internal diode voltage drop I
BOOT
= 5 mA 0.7 1 V
I
BOOT(lk)
BOOT diode leakage current
(6)
(V
BOOT
– V
SW
) = 6 V 1 μA
UVLO
VDD UVLO turn on threshold
(7)
Factory default settings (minimum) 2.475 2.750 3.025
V
UVLO(on)
V
2.25 V ≤ V
VDD
≤ 20 V,
Accuracy
(7)
–10% 10%
2.75 V ≤ VIN_ON ≤ 18 V
VDD UVLO turn off threshold
(7)
Factory default settings (minimum) 2.25 2.5 2.75
V
UVLO(off)
V
2.25 V < V
VDD
< 20 V,
Accuracy
(7)
–10% 10%
2.75 V < VIN_OFF < 17.6 V
REMOTE VOLTAGE SENSE AMPLIFIER
V
IOFST
Input offset voltage –10 10 mV
R
GAIN
Gain setting resistor
(6)
48 60 72 kΩ
V
VDD
> 6.5 V 0 6
V
DIFFO
Output voltage at DIFFO pin V
VDD
= 5 V 0 4.5 V
V
VDD
= 3 V 0 2.5
K
DIFF
Differential gain of amplifier 0.995 1.000 1.005 V/V
V
AGBWP
Closed loop bandwidth
(6)
2 MHz
I
VAOP
Output source current V
SNS+
= V
DIFFO
= 5 V, V
SNS–
= 0 V 1 mA
I
VAOM
Output sink current V
SNS+
= 0 V, V
SNS–
= 4.5 V, V
DIFFO
= 5 V 1 mA
POWERGOOD
FB pin voltage upper limit for power good on 648
Factory default settings mV
V
PGON
FB pin voltage lower limit for power good on 552
Accuracy 540 mV < V
PGON
< 660 mV –5% 5%
FB pin voltage upper limit for power good off 660 mV
Factory default settings
V
PGOFF
FB pin voltage lower limit for power good off 540
Accuracy 528 mV < V
PGOFF
< 672 mV –5% 5%
R
PGD
Pull down resistance of PGD pin V
FB
= 0, I
PGOOD
= 5 mA 50 Ω
Factory default settings ,
I
PGDLK
Leakage current 3 15 μA
550 mV < V
FB
< 650 mV, V
PGOOD
= 5 V
t
PGD
Delay filter from FB
(6)
5 μs
(6) Ensured by design. Not production tested.
(7) Although specifications appear to overlap, hysteresis is assured for UVLO turn on and turn off thresholds.
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