Datasheet
TPS40303, TPS40304, TPS40305
SLUS964A –NOVEMBER 2009–REVISED AUGUST 2012
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
T
J
= –40°C to 125°C, V
VDD
= 12 V, all parameters at zero power dissipation (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PGOOD
Feedback upper voltage limit for
V
OV
655 675 700
PGOOD
Feedback lower voltage limit for mV
V
UV
500 525 550
PGOOD
V
PGD-HYST
PGOOD hysteresis voltage at FB 25 40
R
PGD
PGOOD pull down resistance V
FB
= 0 V, I
FB
= 5 mA 30 70 Ω
550 mV < V
FB
< 655 mV,
I
PGDLK
PGOOD leakage current 10 20 µA
V
PGOOD
= 5 V
OUTPUT DRIVERS
R
HDHI
High-side driver pull-up resistance V
BOOT
– V
SW
= 5 V, I
HDRV
= –100 mA 0.8 1.5 2.5 Ω
R
HDLO
High-side driver pull-down resistance V
BOOT
– V
SW
= 5 V, I
HDRV
= 100 mA 0.5 1.0 2.2 Ω
R
LDHI
Low-side driver pull-up resistance I
LDRV
= -100 mA 0.8 1.5 2.5 Ω
R
LDLO
Low-side driver pull-down resistance I
LDRV
= 100 mA 0.35 0.60 1.20 Ω
t
HRISE
(2)
High-side driver rise time C
LOAD
= 5 nF 15 ns
t
HFALL
(2)
High-side driver fall time 12 ns
t
LRISE
(2)
Low-side driver rise time 15 ns
t
LFALL
(2)
Low-side driver fall time 10 ns
OVERCURRENT PROTECTION
t
PSSC(min)
(2)
Minimum pulse time during short circuit 250 ns
t
BLNKH
(2)
Switch leading-edge blanking pulse time 150 ns
V
OCH
OC threshold for high side FET T
J
= 25°C 360 450 580 mV
I
OCSET
OCSET current source T
J
= 25°C 9.5 10.0 10.5 µA
V
LD-CLAMP
Maximum clamp voltage at LDRV 260 340 400 mV
OC comparator offset voltage for low
V
OCLOS
T
J
= 25°C –8 8 mV
side FET
Programmable OC range for low side
V
OCLPRO
(2)
T
J
= 25°C 12 300 mV
FET
OC threshold temperature coefficient
V
THTC
(2)
3000 ppm
(both high side and low side)
t
OFF
OC retry cycles on EN/SS pin 4 Cycle
BOOT DIODE
V
DFWD
Bootstrap diode forward voltage I
BOOT
= 5 mA 0.8 V
THERMAL SHUTDOWN
T
JSD
(2)
Junction shutdown temperature 145 °C
T
JSDH
(2)
Hysteresis 20 °C
(2) Ensured by design. Not production tested.
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