Datasheet

FB
OUT FB
V R4
0.600 V 10.0 k
R5 5.0 k 4.99 k
V V 1.8 V 0.600 V
´
´ W
= = = W » W
- -
OC OCLOS(min)
CS
OCSET(min)
V V
62.1mV ( 8mV)
R 3.69k 3.74k
2 I 2 9.5 A
-
- -
= = = W » W
´ ´ m
( )
1 1
OC LOAD RIPPLE
DS on Q1
2 2
V (1.3 I I ) 1.2 R (1.3 10 A 3.5 A) 1.2 4.6m 62.1mV= ´ - ´ ´ = ´ - ´ ´ W =
BP G1 G2
C 100 MAX(Q ,Q )= ´
TPS40303, TPS40304, TPS40305
www.ti.com SLUS964A –NOVEMBER 2009–REVISED AUGUST 2012
(15)
Since Q1 is larger than Q2, and the total gate charge of Q1 is 10 nC, a BP capacitor of 1.0 µF is calculated. A
standard value of 1.0 µF is selected to limit noise on the BP regulator.
Short Circuit Protection (R11)
The TPS40305 uses the negative drop across the low-side FET at the end of the OFF time to measure the
inductor current. Allowing for 30% over maximum load and 20% rise in R
DS(on)Q1
for self-heating, the voltage drop
across the low-side FET at current limit is given by Equation 16.
(16)
The TPS40305 internal temperature coefficient helps compensate for the MOSFET’s R
DS(on)
temperature
coefficient, so the current limit programming resistor is selected by Equation 17.
(17)
Feedback Divider (R4, R5)
The TPS40305 controller uses a full operational amplifier with an internally fixed 0.600-V reference. R4 is
selected between 10 kΩM and 50 kΩ for a balance of feedback current and noise immunity. With R4 set to 10
kΩ, The output voltage is programmed with a resistor divider given by Equation 18.
(18)
Compensation: (C2, C3, C4, R3, R6)
Using the TPS40k Loop Stability Tool for 100 kHz bandwidth and 60° phase margin with a R4 value of 10.0 kΩ,
the following values are returned.
• C2 = C_1 = 820 pF
• C3 = C_3 = 150 pF
• C4 = C_2 = 3300 pF
• R3 = R_2 = 422 Ω
• R6 = R_3 = 2.20 kΩ
Design Example Typical Performance Characteristics
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