Datasheet

= ´ = ´ =
BOOST G2
C 20 Q 20 5nC 100nF
( )
( )
LOAD RMS
RMS cin
I I D 1 D 10 A 0.225 (1 0.225) 4.17 A = ´ ´ - = ´ ´ - =
RIPPLE(esr )
MAX
1
LOAD RIPPLE
2
V
150 mV
ESR 12.7 m
I I 11.75 A
= = = W
+
LOAD OUT
IN(min)
RIPPLE(cap) IN SW
I V
10 1.8 V
C 12.5 F
V V f 150mV 8 V 1200kHz
´
´
= = = m
´ ´ ´ ´
( )
1 1
OUT(max) RIPPLE CHARGE
L peak
2 2
I I I I 10 A 3.5 A 0.053 A 11.8 A= + + = + ´ + =
OUT OUT
CHARGE
SS
V C
1.8 V 2 22 F
I 0.053 A
t 1.5ms
´
´ ´ m
= = =
TPS40303, TPS40304, TPS40305
SLUS964A –NOVEMBER 2009–REVISED AUGUST 2012 www.ti.com
Peak Current Rating of Inductor
With output capacitance, it is possible to calculate the charge current during start-up and determine the minimum
saturation current rating for the inductor. The start-up charging current is approximated by Equation 9.
(9)
(10)
Table 2. Inductor Requirements
SYMBOL PARAMETER VALUE UNITS
L Inductance 400 nH
I
L(rms)
RMS current (thermal rating) 10.05 A
I
L(peak)
Peak current (saturation rating) 11.8 A
A PG0083.401, 400 nH inductor is selected for its small size, low DCR (3.0mΩ) and high-current handling
capability (17-A thermal, 27-A saturation).
Input Capacitor Selection (C8)
The input voltage ripple is divided between capacitance and ESR. For this design V
RIPPLE(cap)
= 150 mV and
V
RIPPLE(esr)
= 150 mV. The minimum capacitance and maximum ESR are estimated by Equation 11.
(11)
(12)
The RMS current in the input capacitors is estimated by Equation 13.
(13)
Two 1210, 10-µF, 25-V, X5R ceramic capacitors with approximately 2-mΩ of ESR and a 2.5-A RMS current
rating each are selected. Higher voltage capacitors are selected to minimize capacitance loss at the DC bias
voltage to ensure the capacitors allow sufficient capacitance at the working voltage.
MOSFET Switch Selection (Q1 and Q2)
Reviewing available TI NexFET MOSFETs using TI’s NexFET MOSFET selection tool, the CSD16410Q5A and
CSD16322Q5 5 mm × 6 mm MOSFETs are selected.
These two FETs have maximum total gate charges of 5 nC and 10 nC respectively, which draws 18 mA at 1.2
MHz from the BP regulator, less than its 50 mA minimum rating.
Bootstrap Capacitor (C6)
To ensure proper charging of the high-side FET gate, limit the ripple voltage on the boost capacitor to less than
50 mV.
(14)
VDD Bypass Capacitor (C7)
Per the TPS40305 Electrical Characteristics specifications, select a 1.0-µF X5R or better ceramic bypass
capacitor for VDD.
BP Bypass Capacitor (C5)
As listed in the Electrical Characteristics table, a minimum of 1.0-µF ceramic capacitance is required to stabilize
the BP regulator. To limit regulator noise to less than 10 mV, the value of the bypass capacitor is calculated in
Equation 15.
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