Datasheet

www.ti.com
1
DRP PACKAGE
(BOTTOM VIEW)
2
3
6
5
4
BOOST
AVIN
PVIN
FB
SW
GND
TPS40222
SLUS642A – OCTOBER 2005 – REVISED JANUARY 2006
A. Exposed pad provides a low thermal resistance of θ
JC
= 2 ° C/W
B. Connect exposed pad to GND.
Table 1. TERMINAL FUNCTIONS
TERMINAL
I/O DESCRIPTION
NAME NO.
Input power to the control section of the device. Closely bypass this pin to GND with a low ESR ceramic capacitor
AVIN 5 I
of 1-µF or greater.
This pin provides a bootstrapped supply for the high-side MOSFET driver for PWM, enabling the gate of the
BOOST 6 I/O high-side MOSFET to be driven above the input supply rail. Connect a 33-nF capacitor from this pin to SW pin and
(optionally) a Schottky diode from this pin to the PVIN pin.
Inverting input of the error amplifier. In closed-loop operation, the voltage at this pin is the internal reference level
of 800 mV. During startup or fault conditions, the voltage on this pin also affects the operating frequency of the
FB 1 I converter. With 0 V on the pin, the operating frequency is approximately 140 kHz.The frequency increases linearly
to approximately 1.25 MHz as the voltage on the pin is raised to 0.6 V. Above 0.6 V, the operating frequency
remains at approximately 1.25 MHz.
GND 2 - Ground connection to the device.
PVIN 4 I Input to the power section of the device. Bypass this pin to GND with a low ESR capacitor of 10-µF or greater.
The source connection of the internal switching MOSFET. Connect this pin to the output inductor and an external
SW 3 I/O
catch diode to form the converter's switch node.
4