Datasheet

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PC BOARD LAYOUT RECOMMENDATIONS

Device Pad Design

PCB Layout

1 2 3

5 4

AVIN PVIN

FB GND SW

BOOST

OUT

UDG−04134

TPS40222

SLUS642A – OCTOBER 2005 – REVISED JANUARY 2006

The 6-pin package has an exposed thermal pad intended to help conduct heat out of the package, allowing a

higher than otherwise available operating ambient temperature. Place three vias within the pad area, tying them

to an analog ground plane.

When designing a DC-to-DC converter layout, care must be taken to ensure a noise-free design.

Figure 21. Ensuring a Noise-Free Layout

• AC current loops must be kept as short as possible. The input loop B (C1-U1-D1) in the figure must be kept

short to ensure proper filtering by C1 for the device. Excessive high frequency noise on AVIN during

switching could degrade overall regulation as the load increases. In order to reduce noise spikes seen by the

device, an R-C filter is recommended (see AVIN Filtering in the APPLICATION INFORMATION section) and

a snubber may be added (see SW Node Snubber in the APPLICATION INFORMATION section).

• The output loop A (D1-L1-C3) should also be kept as small as possible. Noise performance at the output of

the converter suffers if the loop area is too large.

• It is recommended that traces carrying large AC currents NOT be connected through a ground plane.

Instead, use PCB traces on the top layer to conduct the AC current and use the ground plane as a noise

shield. Split the ground plane as necessary to keep noise away from the TPS40222 and noise sensitive

areas (R1, R2).

• Keep the SW node as physically small as possible to minimize parasitic capacitance and to minimize

radiated emissions

• For good output voltage regulation, R1 should be connected close to the load. The R2-TPS40222 (GND)

connection should be tied close to the load as well.

• The trace from the R1-R2 junction to the TPS40222 should be kept away from any noise source, such as the

SW node, or the boost circuitry.

• The GND pin and the thermal pad of the TPS40222 should be connected together under the device as

indicated in the pad design section. For good thermal conductivity, VIAs directly under the device should

connect the thermal pad to a ground plane on the other side of the board.