Datasheet

V
SSE(1)
V
SS
V
OUT
V
SSE
V
SS(ofst)
t
0
t
1
V
SS(ofst)
+700 mV
V
IN
- V
D
t
2
t
3
2
5
4
SS
COMP
FB
TPS40210/11
R
SS(chg)
UDG-07121
+
+
R
SS(dchg)
700 mV REF
OC Fault
UVLODIS
Error Amplifier
TPS40210-Q1, TPS40211-Q1
www.ti.com SLVS861D –AUGUST 2008–REVISED APRIL 2010
point of zero volts. It cannot do this, due to the converter architecture. The output voltage starts from the input
voltage less the drop across the diode (V
IN
– V
D
) and rises from there. The point at which the output voltage
starts to rise (t
2
) is when the V
SSE
ramp passes the point where it is commanding more output voltage than (V
IN
–
V
D
). This voltage level is labeled V
SSE(1)
. The time required for the output voltage to ramp from a theoretical zero
to the final regulated value (from t
1
to t
3
) is determined by the time it takes for the capacitor connected to the SS
pin (C
SS
) to rise through a 700-mV range, beginning at V
SS(ofst)
above GND.
Figure 24. SS Pin Voltage and Output Voltage Figure 25. SS Pin Functional Circuit
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