Datasheet

V
SSE(1)
V
SS
V
OUT
V
SSE
V
SS(ofst)
t
0
t
1
V
SS(ofst)
+700 mV
V
IN
- V
D
t
2
t
3
2
5
4
SS
COMP
FB
TPS40210/11
R
SS(chg)
UDG-07121
+
+
R
SS(dchg)
700 mV REF
OC Fault
UVLODIS
Error Amplifier
( )
SS
SS
BP SS(ofst)
SS
BP SS(ofst) FB
t
C
V V
R ln
V V V
=
æ ö
-
ç ÷
´
ç ÷
- +
è ø
TPS40210, TPS40211
www.ti.com SLUS772E –MARCH 2008– REVISED OCTOBER 2011
volts. It cannot do this due to the converter architecture. The output voltage starts from the input voltage less the
drop across the diode (V
IN
- V
D
) and rises from there. The point at which the output voltage starts to rise (t
2
) is
the point where the V
SSE
ramp passes the point where it is commanding more output voltage than (V
IN
- V
D
). This
voltage level is labeled V
SSE(1)
. The time required for the output voltage to ramp from a theoretical zero to the
final regulated value (from t
1
to t
3
) is determined by the time it takes for the capacitor connected to the SS pin
(C
SS
) to rise through a 700 mV range, beginning at V
SS(ofst)
above GND.
Figure 24. SS Pin Voltage and Output Voltage Figure 25. SS Pin Functional Circuit
The required capacitance for a given soft start time t
3
– t
1
in Figure 24 is calculated in Equation 13.
(13)
Where:
• t
SS
is the soft-start time, in seconds
• R
SS(chg)
is the SS charging resistance in Ω, typically 500 kΩ
• C
SS
is the value of the capacitor on the SS pin, in F
• V
BP
is the value of the voltage on the BP pin, in V
• V
SS(ofst)
is the approximate level shift from the SS pin to the error amplifier (~700 mV)
• V
FB
is the error amplifier reference voltage, 700mV typical
Note that t
SS
is the time it takes for the output voltage to rise from 0 V to the final output voltage. Also note the
tolerance on R
SS(chg)
given in the electrical specifications table. This contributes to some variability in the output
voltage rise time and margin must be applied to account for it in design.
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