TPS40210, TPS40211 SLUS772E – MARCH 2008 – REVISED OCTOBER 2011 www.ti.com 4.5-V TO 52-V INPUT CURRENT MODE BOOST CONTROLLER Check for Samples: TPS40210, TPS40211 FEATURES CONTENTS 1 • • • • • • • • • • • For Boost, Flyback, SEPIC, LED Drive Apps Wide Input Operating Voltage: 4.
TPS40210, TPS40211 SLUS772E – MARCH 2008 – REVISED OCTOBER 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
TPS40210, TPS40211 SLUS772E – MARCH 2008 – REVISED OCTOBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS TJ = –40°C to 125°C, VVDD= 12 Vdc, all parameters at zero power dissipation (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TPS40210 COMP = FB, 4.5 ≤ VVDD ≤ 52 V, TJ = 25°C 693 700 707 TPS40211 COMP=FB, 4.5 ≤ VVDD ≤ 52 V, TJ = 25°C 254 260 266 COMP = FB, 4.5 ≤ VVDD ≤ 52 V, -40°C ≤ TJ ≤ TPS40210 125°C 686 700 714 COMP = FB, 4.
TPS40210, TPS40211 SLUS772E – MARCH 2008 – REVISED OCTOBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) TJ = –40°C to 125°C, VVDD= 12 Vdc, all parameters at zero power dissipation (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 4..2 5.6 7.
TPS40210, TPS40211 SLUS772E – MARCH 2008 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS FREQUENCY vs TIMING RESISTANCE SWITCHING FREQUENCY vs DUTY CYCLE 68 pF CT(pF) 33pF 470 220 100 68 33 fSW - Frequency - kHz 1000 800 100pF 600 220 pF 400 1200 1000 fSW - Frequency - kHz 1200 200 800 600 400 200 470 pF 0 100 200 300 400 500 600 700 800 RT - Timing Resistance - kW 0 900 1000 0 0.2 0.4 0.6 0.8 D - Duty Cycle Figure 1. Figure 2.
TPS40210, TPS40211 SLUS772E – MARCH 2008 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) REFERENCE VOLTAGE CHANGE vs JUNCTION TEMPERATURE REFERENCE VOLTAGE CHANGE vs INPUT VOLTAGE 0.4 0.5 0.4 0.2 0.0 -0.2 -0.4 -0.6 4.5 V VVDD 12 V 4.5 V 52 V 12 V VFB – Reference Voltage Change – % VFB – Reference Voltage Change – % 52 V 0.2 0.1 0.0 -0.1 -0.2 -0.3 -0.4 -0.8 -40 -25 -10 5 20 35 50 65 80 95 110 125 TJ – Junction Temperature – ° C -0.
TPS40210, TPS40211 SLUS772E – MARCH 2008 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) SWITCHING FREQUENCY CHANGE vs JUNCTION TEMPERATURE 155 5 154 4 fOSC – Switching Frequency Change – % VISNS(OC) – Overcurrent Threshold – mV OVERCURRENT THRESHOLD vs INPUT VOLTAGE 153 152 151 150 149 148 147 146 145 5 10 15 20 25 30 35 VVDD – Input Voltage – V 40 Slope Compensation Ratio (VVDD/VSLP) 4.5 V 1 12 V 0 -1 30 V -2 VVDD (V) 4.5 V 12 V 30 V -3 -4 Figure 9. Figure 10.
TPS40210, TPS40211 SLUS772E – MARCH 2008 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) FB BIAS CURRENT vs JUNCTION TEMPERATURE COMPENSATION SOURCE CURRENT vs JUNCTION TEMPERATURE 180 ICOMP(SRC) – Compensation Source Current – mA 300 IIB(FB) – Feedback Bias Current – nA 160 140 120 100 80 60 40 20 0 -40 -25 -10 5 20 35 50 65 80 95 110 125 TJ – Junction Temperature – ° C 200 150 100 50 0 -40 -25 -10 5 20 35 50 65 80 95 110 125 TJ – Junction Temperature – ° C Figure 13.
TPS40210, TPS40211 SLUS772E – MARCH 2008 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) REGULATOR VOLTAGE vs JUNCTION TEMPERATURE DIS/EN TURN-ON THRESHOLD vs JUNCTION TEMPERATURE 1.10 8.8 VDIS(EN) – DIS/EN Turn-On Threshold – mV 1.09 VBP – Regulator Voltage – V 8.6 1.08 ILOAD = 0 mA 8.4 1.07 1.06 8.2 1.05 8.0 7.8 1.06 1.03 ILOAD = 5 mA 1.02 7.6 1.01 7.4 -40 -25 -10 5 20 35 50 65 80 95 110 125 TJ – Junction Temperature – ° C 1.
TPS40210, TPS40211 SLUS772E – MARCH 2008 – REVISED OCTOBER 2011 www.ti.com DEVICE INFORMATION TERMINAL FUNCTIONS TERMINAL I/O DESCRIPTION 4 O Error amplifier output. Connect control loop compensation network between COMP pin and FB pin. DIS/EN 3 I Disable pin. Pulling this pin high, places the part into a shutdown mode. Shutdown mode is characterized by a very low quiescent current. While in shutdown mode, the functionality of all blocks is disabled and the BP regulator is shut down.
TPS40210, TPS40211 SLUS772E – MARCH 2008 – REVISED OCTOBER 2011 www.ti.
TPS40210, TPS40211 SLUS772E – MARCH 2008 – REVISED OCTOBER 2011 www.ti.com APPLICATION INFORMATION Minimum On-Time and Off Time Considerations The TPS40210 has a minimum off time of approximately 200 ns and a minimum on time of 300 ns. These two constraints place limitations on the operating frequency that can be used for a given input to output conversion ratio. See Figure 2 for the maximum frequency that can be used for a given duty cycle.
TPS40210, TPS40211 SLUS772E – MARCH 2008 – REVISED OCTOBER 2011 www.ti.com Setting the Oscillator Frequency The oscillator frequency is determined by a resistor and capacitor connected to the RC pin of the TPS40210. The capacitor is charged to a level of approximately VVDD/20 by current flowing through the resistor and is then discharged by a transistor internal to the TPS40210. The required resistor for a given oscillator frequency is found from either Figure 1 or Equation 5. RT = 1 5.
TPS40210, TPS40211 SLUS772E – MARCH 2008 – REVISED OCTOBER 2011 www.ti.com VDD Amplitude > VIN 8 VIN + 20 RRC Duty Cycle < 50% RC Q R Q CLK + 1 Frequency > Controller Frequency + CRC S 150 mV GND 5 TPS40210/11 UDG-08064 Figure 21.
TPS40210, TPS40211 SLUS772E – MARCH 2008 – REVISED OCTOBER 2011 www.ti.com RISNS = fSW ´ L ´ VISNS(oc) 2 ´ L ´ fSW ´ IOUT(oc) ´ (VOUT + VD - VIN ) (6) If the converter is operating in continuous conduction mode RISNS can be found in Equation 7. RISNS = VISNS VISNS = æ IOUT ö æ IRIPPLE ö æ IOUT ö æ D ´ VIN ö + ç 1- D ÷ + ç 2 ÷ø çç (1 - D ) ÷÷ ç 2 ´ fSW ´ L ÷ è ø è ø è ø è (7) Where: • RISNS is the value of the current sense resistor in Ω.
TPS40210, TPS40211 SLUS772E – MARCH 2008 – REVISED OCTOBER 2011 www.ti.com Since the slope compensation ramp must be at least half, and preferably equal to the down slope of the current sense waveform seen at the pulse width modulator, a maximum value is placed on the current sense resistor when operating in continuous mode at 50% duty cycle or greater. For design purposes, some margin should be applied to the actual value of the current sense resistor.
TPS40210, TPS40211 SLUS772E – MARCH 2008 – REVISED OCTOBER 2011 www.ti.com volts. It cannot do this due to the converter architecture. The output voltage starts from the input voltage less the drop across the diode (VIN - VD) and rises from there. The point at which the output voltage starts to rise (t2) is the point where the VSSE ramp passes the point where it is commanding more output voltage than (VIN - VD). This voltage level is labeled VSSE(1).
TPS40210, TPS40211 SLUS772E – MARCH 2008 – REVISED OCTOBER 2011 www.ti.com Also take note of VBP. Its value varies depending on input conditions. For example, a converter operating from a slowly rising input initializes VBP at a fairly low value and increases during the entire startup sequence. If the controller has a voltage above 8 V at the input and the DIS pin is used to stop and then restart the converter, VBP is approximately 8 V for the entire startup sequence.
TPS40210, TPS40211 SLUS772E – MARCH 2008 – REVISED OCTOBER 2011 www.ti.com VBP VSS tRSTR(min) VSS(ofst) VSS(rst) T - Time Figure 26.
TPS40210, TPS40211 SLUS772E – MARCH 2008 – REVISED OCTOBER 2011 www.ti.com BP Regulator The TPS40210/11 has an on board linear regulator the supplies power for the internal circuitry of the controller, including the gate driver. This regulator has a nominal output voltage of 8 V and must be bypassed with a 1-μF capacitor. If the voltage at the VDD pin is less than 8 V, the voltage on the BP pin will also be less and the gate drive voltage to the external FET is reduced from the nominal 8 V.
TPS40210, TPS40211 SLUS772E – MARCH 2008 – REVISED OCTOBER 2011 www.ti.com Control Loop Considerations There are two methods to design a suitable control loop for the TPS4021x. The first and preferred if equipment is available is to use a frequency response analyzer to measure the open loop modulator and power stage gain and to then design compensation to fit that. The usage of these tools for this purpose is well documented with the literature that accompanies the tool and is not be discussed here.
TPS40210, TPS40211 SLUS772E – MARCH 2008 – REVISED OCTOBER 2011 www.ti.
TPS40210, TPS40211 SLUS772E – MARCH 2008 – REVISED OCTOBER 2011 www.ti.com While the error amplifier GBWP will usually be higher, it can be as low as 1.5 MHz. If 10 × KComp × fL > 1.5 MHz, the error amplifier gain-bandwidth product may limit the high-frequency response below that of the high-frequency capacitor. To maintain a consistent high-frequency gain roll-off, CHF can be calculated by Equation 29. CHF = 1 6 2p ´ 1.
TPS40210, TPS40211 SLUS772E – MARCH 2008 – REVISED OCTOBER 2011 www.ti.com VIN IOUT TPS40210/11 1 RC 2 SS 3 DIS/EN L VDD 10 BP 9 GDRV 8 4 COMP ISNS 7 5 FB GND RIFB 6 UDG-07197 Figure 29. Typical LED Drive Schematic The current in the LED string is set by the choice of the resistor RISNS as shown in Equation 31. RIFB = VFB IOUT (31) Where: • RIFB is the value of the current sense resistor for the LED string in Ω • VFB is the reference voltage for the TPS40211 in V (0.
TPS40210, TPS40211 SLUS772E – MARCH 2008 – REVISED OCTOBER 2011 www.ti.com ADDITIONAL REFERENCES Related Devices The following devices have characteristics similar to the TPS40210 and may be of interest. Table 1. Related Parts DEVICE DESCRIPTION TPS6100X Single- and Dual-Cell Boost Converter with Start-up into Full Load TPS6101X High Efficiency 1-Cell and 2-Cell Boost Converters TPS6300X High Efficiency Single Inductor Buck-Boost Converter with 1.
TPS40210, TPS40211 SLUS772E – MARCH 2008 – REVISED OCTOBER 2011 www.ti.com DESIGN EXAMPLE 1 12-V to 24-V Non-Synchronous Boost Regulator The following example illustrates the design process and component selection for a 12-V to 24-V non-synchronous boost regulator using the TPS40210 controller. + + Figure 30. TPS40210 Design Example – 12-V to 24-V at 2-A Table 2.
TPS40210, TPS40211 SLUS772E – MARCH 2008 – REVISED OCTOBER 2011 www.ti.com Table 2. TPS40210 Design Example Specifications (continued) PARAMETER CONDITIONS MIN NOM MAX UNIT 600 kHz SYSTEM CHARACTERISTICS fSW Switching frequency ηPK Peak efficiency VIN = 12 V 95% η Full load efficiency VIN = 12 V, IOUT = 2 A 94% TOP Operating temperature range 8 V ≤ VIN ≤ 14 V, IOUT ≤ 2 A °C 25 MECHANICAL DIMENSIONS W Width 1.5 L Length 1.5 h Height 0.
TPS40210, TPS40211 SLUS772E – MARCH 2008 – REVISED OCTOBER 2011 www.ti.com A 10-μH inductor with a minimum RMS current rating of 6.13 A and minimum saturation current rating of 6.57 A must be selected. A TDK RLF12560T-100M-7R5 7.5-A 10-μH inductor is selected. This inductor power dissipation is estimated by Equation 40. 2 PL » (ILrms ) ´ DCR (40) The TDK RLF12560T-100M-7R5 12.4-mΩ DCR dissipates 466 mW of power.
TPS40210, TPS40211 SLUS772E – MARCH 2008 – REVISED OCTOBER 2011 www.ti.com Current Sense and Current Limit The maximum allowable current sense resistor value is limited by both the current limit and sub-harmonic stability. These two limitations are given by Equation 49 and Equation 50. VISNS(OC)MIN 120mV = = 15.4mW RISNS < ´ 1.1 (6.57 A + 0.50 A) 1.1´ IL(peak ) + IDrive ( ) (49) VIN(MAX) ´ L ´ fSW 14 V ´ 10 mH ´ 600kHz RISNS < = = 134mW 60 ´ (VOUT + VFD - VIN ) 60 ´ (24 V + 0.
TPS40210, TPS40211 SLUS772E – MARCH 2008 – REVISED OCTOBER 2011 www.ti.com Feedback Divider Resistors The primary feedback divider resistor (RFB) from VOUT to FB should be selected between 10-kΩ and 100-kΩ to maintain a balance between power dissipation and noise sensitivity. For a 24-V output a high feedback resistance is desirable to limit power dissipation so RFB = 51.1 kΩ is selected. RBIAS = VFB ´ RFB 0.700 V ´ 51.1kW = = 1.53kW VOUT - VFB 24 V - 0.700 V (57) RBIAS = 1.50 kΩ is selected.
TPS40210, TPS40211 SLUS772E – MARCH 2008 – REVISED OCTOBER 2011 www.ti.com C2 = 10 10 = = 2837pF 2p ´ fL ´ R4 2p ´ 30kHz ´ 18.7kW (65) C2 = 2200 pF selected. Place a high-frequency pole at about 5 times the desired cross-over frequency and less than one-half the unity gain bandwidth of the error amplifier: C4 » C4 > 1 1 = = 56.74pF 10p ´ fL ´ R4 10p ´ 30kHz ´ 18.7kW (66) 1 1 = = 11.35pF p ´ GBW ´ R4 p ´ 1.5MHz ´ 18.7kW (67) C4 = 47 pF selected.
TPS40210, TPS40211 SLUS772E – MARCH 2008 – REVISED OCTOBER 2011 www.ti.com EFFICIENCY vs LOAD CURRENT POWER LOSS vs LOAD CURRENT 6 100 VIN (V) 14 12 8 96 5 h – Efficiency – % 94 92 VIN = 12 V 90 88 VIN = 8 V 86 VIN = 8 V VIN (V) 14 12 8 VIN = 14V PLOSS – Power Loss – W 98 4 VIN = 12 V 3 2 VIN = 14 V 84 1 82 80 0 0 0.5 1.0 1.5 2.0 ILOAD – Load Current – A 2.5 0 0.5 Figure 33. 1.0 1.5 2.0 ILOAD – Load Current – A 2.5 Figure 34. OUTPUT VOLTAGE vs LOAD CURRENT 24.
TPS40210, TPS40211 SLUS772E – MARCH 2008 – REVISED OCTOBER 2011 www.ti.com Table 3. List of Materials (continued) REFERENCE DESIGNATOR DESCRIPTION SIZE PART NUMBER MANUFACTURER C2 2200 pF, ceramic capacitor, 25 V, X7R, 20% 0603 Std Std C3 100 pF, ceramic capacitor, 16 V, C0G, 10% 0603 Std Std C4 47 pF, ceramic capacitor, 16V, X7R, 20% 0603 Std Std C5 0.22 μF, ceramic capacitor, 16 V, X7R, 20% 0603 Std Std C7 1.
TPS40210, TPS40211 SLUS772E – MARCH 2008 – REVISED OCTOBER 2011 www.ti.com DESIGN EXAMPLE 2 12-V Input, 700-mA LED Driver, Up to 35-V LED String Application Schematic L1 VIN C21 C1 GDRV C2 D1 B2100 Q1 R2 R11 ISNS C3 R1 C4 VIN R3 D2 C8 1 U1 TPS40211 RC VIN 10 C10 C9 Loop Response Injection R23 C6 R13 R4 DIS/EN C11 2 SS BP 9 3 DIS/EN GDRV 8 4 COMP ISNS 7 5 FB GND 6 GDRV ISNS C5 LEDC LEDC C13 R24 R6 D3 R15 Q3 C14 PWM Dimming UDG-08015 Figure 36.
TPS40210, TPS40211 SLUS772E – MARCH 2008 – REVISED OCTOBER 2011 www.ti.com List of Materials Table 4. List of Materials REFERENCE DESIGNATOR TYPE DESCRIPTION SIZE C1,C2 10 μF, 25 V 1206 C3, C4 2.2 μF, 100 V 1210 C5 1 nF, NPO 0603 C6 100 pF, NPO 0603 C8 100 pF 0603 0.1 μF 0603 C10 0.
TPS40210, TPS40211 SLUS772E – MARCH 2008 – REVISED OCTOBER 2011 www.ti.com REVISION HISTORY Changes from Revision C (October 2008) to Revision D Page • Changed CISNS to CIFLT ....................................................................................................................................................... 16 • Changed CISNS to CIFLT ......................................................................................................................................................
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE OPTION ADDENDUM www.ti.com 10-Jun-2014 PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details.
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS40210DGQR MSOPPower PAD DGQ 10 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TPS40210DGQR MSOPPower PAD DGQ 10 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1 TPS40210DRCR SON DRC 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS40210DGQR MSOP-PowerPAD DGQ 10 2500 364.0 364.0 27.0 TPS40210DGQR MSOP-PowerPAD DGQ 10 2500 346.0 346.0 35.0 TPS40210DRCR SON DRC 10 3000 367.0 367.0 35.0 TPS40210DRCT SON DRC 10 250 210.0 185.0 35.0 TPS40211DGQR MSOP-PowerPAD DGQ 10 2500 364.0 364.0 27.0 TPS40211DRCR SON DRC 10 3000 367.
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