Datasheet

D P
(TOP VIEW)
ACKAGE
ISNS
GDRV
VDD
SS
RC
COMP
FB
GND
1
2
3
4
8
7
6
5
COMP
FB
SS
ISNS
RC
Soft-Start
and
Overcurrent
E/A andSS
Reference
EnableE/A
700mV
PWM
Logic
GDRVvoltage
swinglimited
to(V – 8V)
IN
TPS40200
VDD
GDRV
GND
+
–
+
Driver
OSC
UVLO
5
3
4
2
7
1
8
6
TPS40200-Q1
SLUS739E –SEPTEMBER 2006–REVISED JULY 2013 www.ti.com
DEVICE INFORMATION
Figure 3. Functional Block Diagram
Figure 4. Device Pinout
TERMINAL FUNCTIONS
TERMINAL
I/O DESCRIPTION
NAME NO.
Switching frequency setting RC network. Connect capacitor from RC pin to GND pin and resistor from V
IN
pin to RC pin. The device may be synchronized to an external clock by connecting an open-drain output to
RC 1 I
this pin and pulling it to GND. The pulse width for synchronization should not be excessive (see General
Information).
Soft-start programming. Connect capacitor from SS to GND to program soft start time. Pulling this pin below
SS 2 I 150 mV causes the output switching to stop, placing the device in a shutdown state. The pin also functions
as a restart timer for overcurrent events.
COMP 3 O Error amplifier output. Connect control loop compensation network from COMP to FB.
FB 4 I Error amplifier inverting input. Connect feedback resistor network center tap to this pin.
GND 5 Device ground
GDRV 6 O Driver output for external P-channel MOSFET
Current-sense comparator input. Connect a current sense resistor between ISNS and V
DD
in order to set
ISNS 7 I
desired overcurrent threshold.
VDD 8 I System input voltage. Connect local bypass capacitor from V
DD
to GND.
4 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated