Datasheet

TPS40200-Q1
SLUS739E –SEPTEMBER 2006–REVISED JULY 2013 www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
For the most current package and ordering information, see the Package Option Addendum at the end of this
document, or see the TI web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
ELECTROSTATIC DISCHARGE (ESD) PROTECTION
MIN MAX UNIT
Human-Body Model (HBM) 1000 V
Charged-Device Model (CDM) 1500 V
Machine Model (MM) 100 V
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
TPS40200 UNIT
V
DD
, ISNS 52
Input voltage range RC, FB –0.3 to 5.5 V
SS –0.3 to 9.0
COMP –0.3 to 9.0
Output voltage range V
GDRV (V
IN
– 10) to V
IN
T
stg
Storage temperature range –55 to 150 °C
Lead temperature 1,6 mm (1/16 in) from case for 10 s 260 °C
RECOMMENDED OPERATING CONDITIONS
MIN MAX UNIT
V
DD
Input voltage 4.5 52 V
T
A
Operating temperature –40 125 °C
THERMAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER TYP UNIT
θ
JC
Thermal resistance, junction to case
(1)
49 °C/W
(1) TI uses test boards designed to JESD 51-3 and JESD 51-7 for thermal-impedance measurements. The parameters outlined in these
standards are also used to set up thermal models. TI uses the thermal-model program ThermCAL, a finite-difference thermal-modeling
tool. Using this test procedure, the junction-to-case thermal resistance of this part is 49°C/W.
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