Datasheet

mW2
2
fVC
P
S
2
MAX_INOSS
COSS
=
××
=
mW22fVQP
SGATEGGATE
=××=
THIN
GGD
CHON
VV
RQ
t
-
´
=
IN
GGD
CHOFF
V
RQ
t
´
=
( )
mW10tIV
2
f
t
I
V
2
f
P
CHOFFpkIN
S
CHON
pk
IN
S
SW
=´´+
÷
÷
ø
ö
ç
ç
è
æ
´´´=
TPS40200-Q1
SLUS739E SEPTEMBER 2006REVISED JULY 2013
www.ti.com
Using the values in this example, the dc power loss is 129 mW. The remaining FET losses are:
P
SW
The power dissipated while switching the FET on and off
P
gate
The power dissipated driving the FET's gate capacitance
P
COSS
The power switching the FET's output capacitance
The total power dissipated by the FET is the sum of these contributions:
P
FET
= P
SW
+ P
gate
+ P
COSS
+ P
RDSON
The P-channel FET used in this application is a FDC654P with the following characteristics:
t
rise
= 13 × 10
–9
C
OSS
= 83 × 10
–12
t
fall
= 6 × 10
–9
Q
g
= 9 nC
R
DSON
= 0.1 V
gate
= 1.9 V
Q
gd
= 1.2 × 10
–9
Q
gs
= 1.0 × 10
–9
Using these device characteristics and the following formulas, P
SW
is calculated as:
(4)
Where and are the switching times for the power FET.
(5)
(6)
I
G
= Q
G
× f
S
= 2.7 mA is the gate current.
The sum of the switching losses is 34 mW and is comparable to the 129-mW dc losses. At added expense, a
slightly larger FET would be better, because the dc loss would drop and the ac losses would increase, with both
moving toward the optimum point of equal losses.
18 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated