Datasheet
8
5
+
1.3V
VDD
GND
200K
-
545k
RUN
TPS40200
+
36K
TPS40200-Q1
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SLUS739E –SEPTEMBER 2006–REVISED JULY 2013
MOSFET Gate Drive
The output driver sinking current is approximately 200 mA and is designed to drive P-channel power FETs. When
the driver pulls the gate charge of the FET it is controlling to –8 V, the drive current folds back to a low level so
that high power dissipation only occurs during the turn-on period of the FET. This feature is particularly valuable
when turning on a FET at high input voltages, where leaving the gate drive current on would otherwise cause
unacceptable power dissipation.
Undervoltage Lockout (UVLO) Protection
UVLO protection ensures proper start-up of the device only when the input voltage has exceeded minimum
operating voltage. Undervoltage protection incorporates hysteresis that eliminates hiccup starting in cases where
input supply impedance is high.
Figure 32. Undervoltage Lockout
Undervoltage protection ensures proper start-up of the device only when the input voltage has exceeded
minimum operating voltage. The UVLO level is measured at the V
DD
pin with respect to GND. Start-up voltage is
typically 4.3 V with approximately 200 mV of hysteresis. The part shuts off at a nominal 4.1 V. As shown in
Figure 32, when the input V
DD
voltage rises to 4.3 V, the 1.3-V comparator threshold voltage is exceeded and a
RUN signal occurs. Feedback from the output closes the switch and shunts the 200-kΩ resistor, so that an
approximately 200-mV lower voltage, or 4.1 V, is required before the part shuts down.
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